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// IP VLNV: xilinx.com:ip:versal_cips:3.4
// IP Revision: 6

(* X_CORE_INFO = "bd_70da,Vivado 2025.1" *)
(* CHECK_LICENSE_TYPE = "design_1_versal_cips_0_0,bd_70da,{}" *)
(* CORE_GENERATION_INFO = "design_1_versal_cips_0_0,bd_70da,{x_ipProduct=Vivado 2025.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=versal_cips,x_ipVersion=3.4,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,PS_PMC_CONFIG=CLOCK_MODE Custom DDR_MEMORY_MODE _Connectivity to DDR via NOC_ DESIGN_MODE 1 PMC_CRP_PL0_REF_CTRL_FREQMHZ 100 PMC_GPIO0_MIO_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 0 .. 25___ PMC_GPIO1_MIO_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 26 .. 51___ PMC_MIO37 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8m\
A_ _OUTPUT_DATA high_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE GPIO__ PMC_OSPI_PERIPHERAL __ENABLE 0_ _IO _PMC_MIO 0 .. 11__ _MODE Single__ PMC_QSPI_COHERENCY 0 PMC_QSPI_FBCLK __ENABLE 1_ _IO _PMC_MIO 6___ PMC_QSPI_PERIPHERAL_DATA_MODE x4 PMC_QSPI_PERIPHERAL_ENABLE 1 PMC_QSPI_PERIPHERAL_MODE _Dual Parallel_ PMC_REF_CLK_FREQMHZ 33.3333 PMC_SD1 __CD_ENABLE 1_ _CD_IO _PMC_MIO 28__ _POW_ENABLE 1_ _POW_IO _PMC_MIO 51__ _RESET_ENABLE 0_ _RESET_IO _PMC_MIO 12__ _WP_ENABLE 0_ _WP_IO _PMC_MIO 1___ PM\
C_SD1_COHERENCY 0 PMC_SD1_DATA_TRANSFER_MODE 8Bit PMC_SD1_PERIPHERAL __CLK_100_SDR_OTAP_DLY 0x3_ _CLK_200_SDR_OTAP_DLY 0x2_ _CLK_50_DDR_ITAP_DLY 0x36_ _CLK_50_DDR_OTAP_DLY 0x3_ _CLK_50_SDR_ITAP_DLY 0x2C_ _CLK_50_SDR_OTAP_DLY 0x4_ _ENABLE 1_ _IO _PMC_MIO 26 .. 36___ PMC_SD1_SLOT_TYPE _SD 3.0_ PMC_USE_NOC_PMC_AXI0 0 PMC_USE_PMC_NOC_AXI0 1 PSPMC_MANUAL_CLK_ENABLE 0 PS_BOARD_INTERFACE ps_pmc_fixed_io PS_CAN1_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 40 .. 41___ PS_ENET0_MDIO __ENABLE 1_ _IO _PS_MIO 24 .. \
25___ PS_ENET0_PERIPHERAL __ENABLE 1_ _IO _PS_MIO 0 .. 11___ PS_ENET1_PERIPHERAL __ENABLE 1_ _IO _PS_MIO 12 .. 23___ PS_GEN_IPI0_ENABLE 1 PS_GEN_IPI0_MASTER A72 PS_GEN_IPI1_ENABLE 1 PS_GEN_IPI2_ENABLE 1 PS_GEN_IPI3_ENABLE 1 PS_GEN_IPI4_ENABLE 1 PS_GEN_IPI5_ENABLE 1 PS_GEN_IPI6_ENABLE 1 PS_I2C0_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 46 .. 47___ PS_I2C1_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 44 .. 45___ PS_MIO19 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL disable_ _SCHMIT\
T 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO21 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL disable_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO7 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL disable_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO9 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL disable_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_NUM_FABRIC_RESETS 1 PS_PCIE_EP_RESET1_IO _PMC_MIO 38_ PS\
_PCIE_EP_RESET2_IO _PMC_MIO 39_ PS_PCIE_RESET _ENABLE 1_ PS_UART0_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 42 .. 43___ PS_USB3_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 13 .. 25___ PS_USE_FPD_CCI_NOC 1 PS_USE_FPD_CCI_NOC0 1 PS_USE_NOC_FPD_AXI0 1 PS_USE_NOC_FPD_CCI0 0 PS_USE_NOC_LPD_AXI0 1 PS_USE_PMCPL_CLK0 1 PS_USE_PMCPL_CLK1 0 PS_USE_PMCPL_CLK2 0 PS_USE_PMCPL_CLK3 0 SMON_ALARMS Set_Alarms_On SMON_ENABLE_TEMP_AVERAGING 0 SMON_TEMP_AVERAGING_SAMPLES 0,PS_PMC_CONFIG_INTERNAL=AURORA_LINE_RATE_GPBS 12.5 BOOT_M\
ODE Custom BOOT_SECONDARY_PCIE_ENABLE 0 CLOCK_MODE Custom COHERENCY_MODE Custom CPM_PCIE0_MODES None CPM_PCIE0_PL_LINK_CAP_MAX_LINK_WIDTH X4 CPM_PCIE0_TANDEM None CPM_PCIE1_MODES None CPM_PCIE1_PL_LINK_CAP_MAX_LINK_WIDTH X4 DDR_MEMORY_MODE _Connectivity to DDR via NOC_ DEBUG_MODE Custom DESIGN_MODE 1 DEVICE_INTEGRITY_MODE Custom DIS_AUTO_POL_CHECK 0 GT_REFCLK_MHZ 156.25 INIT_CLK_MHZ 125 INV_POLARITY 0 IO_CONFIG_MODE Custom JTAG_USERCODE 0x0 OT_EAM_RESP SRST PCIE_APERTURES_DUAL_ENABLE 0 PCIE_APER\
TURES_SINGLE_ENABLE 0 PERFORMANCE_MODE Custom PL_SEM_GPIO_ENABLE 0 PMC_ALT_REF_CLK_FREQMHZ 33.333 PMC_BANK_0_IO_STANDARD LVCMOS1.8 PMC_BANK_1_IO_STANDARD LVCMOS1.8 PMC_CIPS_MODE ADVANCE PMC_CLKMON0_CONFIG __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON0_CONFIG_1 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON0_CONFIG_2 _\
_BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON0_CONFIG_3 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON1_CONFIG __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON1_CONFIG_1 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SE\
L REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON1_CONFIG_2 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON1_CONFIG_3 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON2_CONFIG __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0\
__ PMC_CLKMON2_CONFIG_1 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON2_CONFIG_2 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON2_CONFIG_3 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON3_CONFIG __BASE 10000_ _BASE_CLK_SRC REF_CLK_ \
_CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON3_CONFIG_1 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON3_CONFIG_2 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON3_CONFIG_3 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _TH\
RESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON4_CONFIG __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON4_CONFIG_1 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON4_CONFIG_2 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON4_CONFIG_3 __BASE 100\
00_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON5_CONFIG __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON5_CONFIG_1 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON5_CONFIG_2 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK\
_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON5_CONFIG_3 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON6_CONFIG __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON6_CONFIG_1 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CL\
KMON6_CONFIG_2 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON6_CONFIG_3 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON7_CONFIG __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON7_CONFIG_1 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FRE\
Q 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON7_CONFIG_2 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CLKMON7_CONFIG_3 __BASE 10000_ _BASE_CLK_SRC REF_CLK_ _CLKA_FREQ 1000_ _CLKA_SEL REF_CLK_ _ENABLE 0_ _INTR 0_ _THRESHOLD_L 0_ _THRESHOLD_U 0__ PMC_CORE_SUBSYSTEM_LOAD 10 PMC_CRP_CFU_REF_CTRL_ACT_FREQMHZ 399.999634 PMC_CRP_CFU_REF_CTRL_DIVISOR0 3 PMC_CRP_CFU_REF_CTRL_FR\
EQMHZ 400 PMC_CRP_CFU_REF_CTRL_SRCSEL PPLL PMC_CRP_DFT_OSC_REF_CTRL_ACT_FREQMHZ 400 PMC_CRP_DFT_OSC_REF_CTRL_DIVISOR0 3 PMC_CRP_DFT_OSC_REF_CTRL_FREQMHZ 400 PMC_CRP_DFT_OSC_REF_CTRL_SRCSEL PPLL PMC_CRP_EFUSE_REF_CTRL_ACT_FREQMHZ 100.000000 PMC_CRP_EFUSE_REF_CTRL_FREQMHZ 100.000000 PMC_CRP_EFUSE_REF_CTRL_SRCSEL IRO_CLK/4 PMC_CRP_HSM0_REF_CTRL_ACT_FREQMHZ 32.432404 PMC_CRP_HSM0_REF_CTRL_DIVISOR0 37 PMC_CRP_HSM0_REF_CTRL_FREQMHZ 33.333 PMC_CRP_HSM0_REF_CTRL_SRCSEL PPLL PMC_CRP_HSM1_REF_CTRL_ACT_FRE\
QMHZ 124.999878 PMC_CRP_HSM1_REF_CTRL_DIVISOR0 8 PMC_CRP_HSM1_REF_CTRL_FREQMHZ 133.333 PMC_CRP_HSM1_REF_CTRL_SRCSEL NPLL PMC_CRP_I2C_REF_CTRL_ACT_FREQMHZ 100 PMC_CRP_I2C_REF_CTRL_DIVISOR0 12 PMC_CRP_I2C_REF_CTRL_FREQMHZ 100 PMC_CRP_I2C_REF_CTRL_SRCSEL PPLL PMC_CRP_LSBUS_REF_CTRL_ACT_FREQMHZ 149.999863 PMC_CRP_LSBUS_REF_CTRL_DIVISOR0 8 PMC_CRP_LSBUS_REF_CTRL_FREQMHZ 150 PMC_CRP_LSBUS_REF_CTRL_SRCSEL PPLL PMC_CRP_NOC_REF_CTRL_ACT_FREQMHZ 999.999023 PMC_CRP_NOC_REF_CTRL_DIVISOR0 1 PMC_CRP_NOC_REF_C\
TRL_FREQMHZ 1000 PMC_CRP_NOC_REF_CTRL_SRCSEL NPLL PMC_CRP_NPI_REF_CTRL_ACT_FREQMHZ 299.999725 PMC_CRP_NPI_REF_CTRL_DIVISOR0 4 PMC_CRP_NPI_REF_CTRL_FREQMHZ 300 PMC_CRP_NPI_REF_CTRL_SRCSEL PPLL PMC_CRP_NPLL_CTRL_CLKOUTDIV 4 PMC_CRP_NPLL_CTRL_FBDIV 120 PMC_CRP_NPLL_CTRL_SRCSEL REF_CLK PMC_CRP_NPLL_TO_XPD_CTRL_DIVISOR0 4 PMC_CRP_OSPI_REF_CTRL_ACT_FREQMHZ 200 PMC_CRP_OSPI_REF_CTRL_DIVISOR0 4 PMC_CRP_OSPI_REF_CTRL_FREQMHZ 200 PMC_CRP_OSPI_REF_CTRL_SRCSEL PPLL PMC_CRP_PL0_REF_CTRL_ACT_FREQMHZ 99.999908\
 PMC_CRP_PL0_REF_CTRL_DIVISOR0 12 PMC_CRP_PL0_REF_CTRL_FREQMHZ 100 PMC_CRP_PL0_REF_CTRL_SRCSEL PPLL PMC_CRP_PL1_REF_CTRL_ACT_FREQMHZ 100 PMC_CRP_PL1_REF_CTRL_DIVISOR0 3 PMC_CRP_PL1_REF_CTRL_FREQMHZ 334 PMC_CRP_PL1_REF_CTRL_SRCSEL NPLL PMC_CRP_PL2_REF_CTRL_ACT_FREQMHZ 100 PMC_CRP_PL2_REF_CTRL_DIVISOR0 3 PMC_CRP_PL2_REF_CTRL_FREQMHZ 334 PMC_CRP_PL2_REF_CTRL_SRCSEL NPLL PMC_CRP_PL3_REF_CTRL_ACT_FREQMHZ 100 PMC_CRP_PL3_REF_CTRL_DIVISOR0 3 PMC_CRP_PL3_REF_CTRL_FREQMHZ 334 PMC_CRP_PL3_REF_CTRL_SRCSEL \
NPLL PMC_CRP_PL5_REF_CTRL_FREQMHZ 400 PMC_CRP_PPLL_CTRL_CLKOUTDIV 2 PMC_CRP_PPLL_CTRL_FBDIV 72 PMC_CRP_PPLL_CTRL_SRCSEL REF_CLK PMC_CRP_PPLL_TO_XPD_CTRL_DIVISOR0 2 PMC_CRP_QSPI_REF_CTRL_ACT_FREQMHZ 299.999725 PMC_CRP_QSPI_REF_CTRL_DIVISOR0 4 PMC_CRP_QSPI_REF_CTRL_FREQMHZ 300 PMC_CRP_QSPI_REF_CTRL_SRCSEL PPLL PMC_CRP_SDIO0_REF_CTRL_ACT_FREQMHZ 200 PMC_CRP_SDIO0_REF_CTRL_DIVISOR0 6 PMC_CRP_SDIO0_REF_CTRL_FREQMHZ 200 PMC_CRP_SDIO0_REF_CTRL_SRCSEL PPLL PMC_CRP_SDIO1_REF_CTRL_ACT_FREQMHZ 199.999817 P\
MC_CRP_SDIO1_REF_CTRL_DIVISOR0 6 PMC_CRP_SDIO1_REF_CTRL_FREQMHZ 200 PMC_CRP_SDIO1_REF_CTRL_SRCSEL PPLL PMC_CRP_SD_DLL_REF_CTRL_ACT_FREQMHZ 1199.998901 PMC_CRP_SD_DLL_REF_CTRL_DIVISOR0 1 PMC_CRP_SD_DLL_REF_CTRL_FREQMHZ 1200 PMC_CRP_SD_DLL_REF_CTRL_SRCSEL PPLL PMC_CRP_SWITCH_TIMEOUT_CTRL_ACT_FREQMHZ 1.000000 PMC_CRP_SWITCH_TIMEOUT_CTRL_DIVISOR0 100 PMC_CRP_SWITCH_TIMEOUT_CTRL_FREQMHZ 1 PMC_CRP_SWITCH_TIMEOUT_CTRL_SRCSEL IRO_CLK/4 PMC_CRP_SYSMON_REF_CTRL_ACT_FREQMHZ 299.999725 PMC_CRP_SYSMON_REF_CT\
RL_FREQMHZ 299.999725 PMC_CRP_SYSMON_REF_CTRL_SRCSEL NPI_REF_CLK PMC_CRP_TEST_PATTERN_REF_CTRL_ACT_FREQMHZ 200 PMC_CRP_TEST_PATTERN_REF_CTRL_DIVISOR0 6 PMC_CRP_TEST_PATTERN_REF_CTRL_FREQMHZ 200 PMC_CRP_TEST_PATTERN_REF_CTRL_SRCSEL PPLL PMC_CRP_USB_SUSPEND_CTRL_ACT_FREQMHZ 0.200000 PMC_CRP_USB_SUSPEND_CTRL_DIVISOR0 500 PMC_CRP_USB_SUSPEND_CTRL_FREQMHZ 0.2 PMC_CRP_USB_SUSPEND_CTRL_SRCSEL IRO_CLK/4 PMC_EXTERNAL_TAMPER __ENABLE 0_ _IO _PMC_MIO 12___ PMC_EXTERNAL_TAMPER_1 __ENABLE 0_ _IO None__ PMC_E\
XTERNAL_TAMPER_2 __ENABLE 0_ _IO None__ PMC_EXTERNAL_TAMPER_3 __ENABLE 0_ _IO None__ PMC_GLITCH_CONFIG __DEPTH_SENSITIVITY 1_ _MIN_PULSE_WIDTH 0.5_ _TYPE EFUSE_ _VCC_PMC_VALUE 0.80__ PMC_GLITCH_CONFIG_1 __DEPTH_SENSITIVITY 1_ _MIN_PULSE_WIDTH 0.5_ _TYPE EFUSE_ _VCC_PMC_VALUE 0.80__ PMC_GLITCH_CONFIG_2 __DEPTH_SENSITIVITY 1_ _MIN_PULSE_WIDTH 0.5_ _TYPE EFUSE_ _VCC_PMC_VALUE 0.80__ PMC_GLITCH_CONFIG_3 __DEPTH_SENSITIVITY 1_ _MIN_PULSE_WIDTH 0.5_ _TYPE EFUSE_ _VCC_PMC_VALUE 0.80__ PMC_GPIO0_MIO_PER\
IPHERAL __ENABLE 1_ _IO _PMC_MIO 0 .. 25___ PMC_GPIO1_MIO_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 26 .. 51___ PMC_GPIO_EMIO_PERIPHERAL_ENABLE 0 PMC_GPIO_EMIO_WIDTH 64 PMC_GPIO_EMIO_WIDTH_HDL 64 PMC_GPI_ENABLE 0 PMC_GPI_WIDTH 32 PMC_GPO_ENABLE 0 PMC_GPO_WIDTH 32 PMC_HSM0_CLK_ENABLE 1 PMC_HSM0_CLK_OUT_ENABLE 0 PMC_HSM1_CLK_ENABLE 1 PMC_HSM1_CLK_OUT_ENABLE 0 PMC_I2CPMC_PERIPHERAL __ENABLE 0_ _IO _PMC_MIO 2 .. 3___ PMC_MIO0 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 12mA_ _OUTPUT_DATA default_ _PULL pu\
llup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO1 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 12mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO10 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 12mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO11 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 12mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO12 __AUX_IO 0_ _DIRECTION \
out_ _DRIVE_STRENGTH 12mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO13 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO14 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO15 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow\
_ _USAGE Reserved__ PMC_MIO16 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO17 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO18 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO19 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTP\
UT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO2 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 12mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO20 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO21 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO22 \
__AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO23 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO24 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO25 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCH\
MITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO26 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO27 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO28 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO29 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STR\
ENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO3 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 12mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO30 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO31 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reser\
ved__ PMC_MIO32 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO33 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO34 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO35 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA def\
ault_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO36 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO37 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA high_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE GPIO__ PMC_MIO38 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO39 __AUX_IO 0_ _DIRECTION \
in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO4 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 12mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO40 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO41 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _US\
AGE Reserved__ PMC_MIO42 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO43 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO44 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO45 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA\
 default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO46 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO47 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PMC_MIO48 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Unassigned__ PMC_MIO49 __AUX_IO\
 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Unassigned__ PMC_MIO5 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 12mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO50 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Unassigned__ PMC_MIO51 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1\
_ _SLEW slow_ _USAGE Reserved__ PMC_MIO6 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 12mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO7 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 12mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO8 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 12mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO9 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH \
12mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PMC_MIO_EN_FOR_PL_PCIE 0 PMC_MIO_TREE_PERIPHERALS _QSPI#QSPI#QSPI#QSPI#QSPI#QSPI#Loopback Clk#QSPI#QSPI#QSPI#QSPI#QSPI#QSPI#USB 2.0#USB 2.0#USB 2.0#USB 2.0#USB 2.0#USB 2.0#USB 2.0#USB 2.0#USB 2.0#USB 2.0#USB 2.0#USB 2.0#USB 2.0#SD1/eMMC1#SD1/eMMC1#SD1#SD1/eMMC1#SD1/eMMC1#SD1/eMMC1#SD1/eMMC1#SD1/eMMC1#SD1/eMMC1#SD1/eMMC1#SD1/eMMC1#GPIO 1#PCIE#PCIE#CANFD1#CANFD1#UART 0#UART 0#LPD_I2C1#LPD_I2C1#LPD_I2C0#LPD_I2C0####\
SD1/eMMC1#Gem0#Gem0#Gem0#Gem0#Gem0#Gem0#Gem0#Gem0#Gem0#Gem0#Gem0#Gem0#Gem1#Gem1#Gem1#Gem1#Gem1#Gem1#Gem1#Gem1#Gem1#Gem1#Gem1#Gem1#Gem0#Gem0_ PMC_MIO_TREE_SIGNALS qspi0_clk#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_io[0]#qspi0_cs_b#qspi_lpbk#qspi1_cs_b#qspi1_io[0]#qspi1_io[1]#qspi1_io[2]#qspi1_io[3]#qspi1_clk#usb2phy_reset#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_tx_data[2]#ulpi_tx_data[3]#ulpi_clk#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_dir#ulpi_stp#ulpi_nxt#clk#dir1/dat\
a[7]#detect#cmd#data[0]#data[1]#data[2]#data[3]#sel/data[4]#dir_cmd/data[5]#dir0/data[6]#gpio_1_pin[37]#reset1_n#reset2_n#phy_tx#phy_rx#rxd#txd#scl#sda#scl#sda####buspwr/rst#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem0_mdc#gem0_\
mdio PMC_NOC_PMC_ADDR_WIDTH 64 PMC_NOC_PMC_DATA_WIDTH 128 PMC_OSPI_COHERENCY 0 PMC_OSPI_PERIPHERAL __ENABLE 0_ _IO _PMC_MIO 0 .. 11__ _MODE Single__ PMC_OSPI_ROUTE_THROUGH_FPD 0 PMC_OT_CHECK __DELAY 0_ _ENABLE 1__ PMC_PL_ALT_REF_CLK_FREQMHZ 33.333 PMC_PMC_NOC_ADDR_WIDTH 64 PMC_PMC_NOC_DATA_WIDTH 128 PMC_QSPI_BAUD_RATE_DIV 8 PMC_QSPI_COHERENCY 0 PMC_QSPI_FBCLK __ENABLE 1_ _IO _PMC_MIO 6___ PMC_QSPI_PERIPHERAL_DATA_MODE x4 PMC_QSPI_PERIPHERAL_ENABLE 1 PMC_QSPI_PERIPHERAL_MODE _Dual Parallel_ PMC_Q\
SPI_ROUTE_THROUGH_FPD 0 PMC_RAM_CFU_REF_CTRL_CSCAN_ACT_FREQMHZ 100 PMC_RAM_CFU_REF_CTRL_CSCAN_DIVISOR0 3 PMC_RAM_CFU_REF_CTRL_CSCAN_FREQMHZ 300 PMC_RAM_CFU_REF_CTRL_CSCAN_SRCSEL PPLL PMC_REF_CLK_FREQMHZ 33.3333 PMC_SD0 __CD_ENABLE 0_ _CD_IO _PMC_MIO 24__ _POW_ENABLE 0_ _POW_IO _PMC_MIO 17__ _RESET_ENABLE 0_ _RESET_IO _PMC_MIO 17__ _WP_ENABLE 0_ _WP_IO _PMC_MIO 25___ PMC_SD0_COHERENCY 0 PMC_SD0_DATA_TRANSFER_MODE 4Bit PMC_SD0_PERIPHERAL __CLK_100_SDR_OTAP_DLY 0x00_ _CLK_200_SDR_OTAP_DLY 0x00_ _CL\
K_50_DDR_ITAP_DLY 0x00_ _CLK_50_DDR_OTAP_DLY 0x00_ _CLK_50_SDR_ITAP_DLY 0x00_ _CLK_50_SDR_OTAP_DLY 0x00_ _ENABLE 0_ _IO _PMC_MIO 13 .. 25___ PMC_SD0_ROUTE_THROUGH_FPD 0 PMC_SD0_SLOT_TYPE _SD 2.0_ PMC_SD0_SPEED_MODE _default speed_ PMC_SD1 __CD_ENABLE 1_ _CD_IO _PMC_MIO 28__ _POW_ENABLE 1_ _POW_IO _PMC_MIO 51__ _RESET_ENABLE 0_ _RESET_IO _PMC_MIO 12__ _WP_ENABLE 0_ _WP_IO _PMC_MIO 1___ PMC_SD1_COHERENCY 0 PMC_SD1_DATA_TRANSFER_MODE 8Bit PMC_SD1_PERIPHERAL __CLK_100_SDR_OTAP_DLY 0x3_ _CLK_200_SDR_\
OTAP_DLY 0x2_ _CLK_50_DDR_ITAP_DLY 0x36_ _CLK_50_DDR_OTAP_DLY 0x3_ _CLK_50_SDR_ITAP_DLY 0x2C_ _CLK_50_SDR_OTAP_DLY 0x4_ _ENABLE 1_ _IO _PMC_MIO 26 .. 36___ PMC_SD1_ROUTE_THROUGH_FPD 0 PMC_SD1_SLOT_TYPE _SD 3.0_ PMC_SD1_SPEED_MODE _high speed_ PMC_SHOW_CCI_SMMU_SETTINGS 0 PMC_SMAP_PERIPHERAL __ENABLE 0_ _IO _32 Bit___ PMC_TAMPER_EXTMIO_ENABLE 0 PMC_TAMPER_EXTMIO_ERASE_BBRAM 0 PMC_TAMPER_EXTMIO_RESPONSE _SYS INTERRUPT_ PMC_TAMPER_GLITCHDETECT_ENABLE 0 PMC_TAMPER_GLITCHDETECT_ENABLE_1 0 PMC_TAMPER_\
GLITCHDETECT_ENABLE_2 0 PMC_TAMPER_GLITCHDETECT_ENABLE_3 0 PMC_TAMPER_GLITCHDETECT_ERASE_BBRAM 0 PMC_TAMPER_GLITCHDETECT_ERASE_BBRAM_1 0 PMC_TAMPER_GLITCHDETECT_ERASE_BBRAM_2 0 PMC_TAMPER_GLITCHDETECT_ERASE_BBRAM_3 0 PMC_TAMPER_GLITCHDETECT_RESPONSE _SYS INTERRUPT_ PMC_TAMPER_GLITCHDETECT_RESPONSE_1 _SYS INTERRUPT_ PMC_TAMPER_GLITCHDETECT_RESPONSE_2 _SYS INTERRUPT_ PMC_TAMPER_GLITCHDETECT_RESPONSE_3 _SYS INTERRUPT_ PMC_TAMPER_JTAGDETECT_ENABLE 0 PMC_TAMPER_JTAGDETECT_ENABLE_1 0 PMC_TAMPER_JTAGDE\
TECT_ENABLE_2 0 PMC_TAMPER_JTAGDETECT_ENABLE_3 0 PMC_TAMPER_JTAGDETECT_ERASE_BBRAM 0 PMC_TAMPER_JTAGDETECT_ERASE_BBRAM_1 0 PMC_TAMPER_JTAGDETECT_ERASE_BBRAM_2 0 PMC_TAMPER_JTAGDETECT_ERASE_BBRAM_3 0 PMC_TAMPER_JTAGDETECT_RESPONSE _SYS INTERRUPT_ PMC_TAMPER_JTAGDETECT_RESPONSE_1 _SYS INTERRUPT_ PMC_TAMPER_JTAGDETECT_RESPONSE_2 _SYS INTERRUPT_ PMC_TAMPER_JTAGDETECT_RESPONSE_3 _SYS INTERRUPT_ PMC_TAMPER_SUP0 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 0_ _TH_HIGH \
0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP0_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 0_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP0_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 0_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP0_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 0_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP1 __ADC_MODE none_ _AVG\
_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 1_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP10 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 10_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP10_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 10_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP10_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 10_ \
_TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP10_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 10_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP11 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 11_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP11_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 11_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ \
PMC_TAMPER_SUP11_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 11_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP11_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 11_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP12 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 12_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP12_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_\
 _SUPPLY_NUM 12_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP12_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 12_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP12_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 12_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP13 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 13_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_\
 _VOLTAGE none__ PMC_TAMPER_SUP13_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 13_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP13_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 13_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP13_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 13_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP14 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N \
none_ _IO_P none_ _SUPPLY_NUM 14_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP14_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 14_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP14_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 14_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP14_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 14_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOL\
TAGE none__ PMC_TAMPER_SUP15 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 15_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP15_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 15_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP15_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 15_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP15_3 __ADC_MODE none_ _AVG_ENABLE 0\
_ _ENABLE 0_ _SUPPLY_NUM 15_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP16 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 16_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP16_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 16_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP16_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 16_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0\
_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP16_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 16_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP17 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 17_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP17_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 17_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP17_2 __ADC_MODE no\
ne_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 17_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP17_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 17_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP18 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 18_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP18_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 18_ _TH_HIGH 0_ _TH\
_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP18_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 18_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP18_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 18_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP19 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 19_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP1\
9_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 19_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP19_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 19_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP19_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 19_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP1_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 1_ _TH_HIGH 0_ _TH_LOW 0_\
 _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP1_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 1_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP1_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 1_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 2_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP20 __ADC_MODE \
none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 20_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP20_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 20_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP20_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 20_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP20_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 20_ _TH_HIGH 0_\
 _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP21 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 21_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP21_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 21_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP21_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 21_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_\
SUP21_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 21_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP22 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 22_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP22_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 22_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP22_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NU\
M 22_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP22_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 22_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP23 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 23_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP23_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 23_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE n\
one__ PMC_TAMPER_SUP23_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 23_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP23_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 23_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP24 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 24_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP24_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENA\
BLE 0_ _SUPPLY_NUM 24_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP24_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 24_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP24_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 24_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP25 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 25_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_\
MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP25_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 25_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP25_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 25_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP25_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 25_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP26 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ \
_IO_N none_ _IO_P none_ _SUPPLY_NUM 26_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP26_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 26_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP26_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 26_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP26_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 26_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0\
_ _VOLTAGE none__ PMC_TAMPER_SUP27 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 27_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP27_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 27_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP27_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 27_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP27_3 __ADC_MODE none_ _AVG_EN\
ABLE 0_ _ENABLE 0_ _SUPPLY_NUM 27_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP28 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 28_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP28_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 28_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP28_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 28_ _TH_HIGH 0_ _TH_LOW 0_ _TH\
_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP28_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 28_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP29 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 29_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP29_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 29_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP29_2 __ADC_M\
ODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 29_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP29_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 29_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP2_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 2_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP2_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 2_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _\
TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP2_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 2_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 3_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP30 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 30_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP30_\
1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 30_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP30_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 30_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP30_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 30_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP31 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 31_ \
_TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP31_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 31_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP31_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 31_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP31_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 31_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP3_1 __AD\
C_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 3_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP3_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 3_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP3_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 3_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP4 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 4_ _TH_HIGH 0_ _\
TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP4_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 4_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP4_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 4_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP4_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 4_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP5 __ADC_MODE none_ _AVG_ENA\
BLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 5_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP5_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 5_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP5_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 5_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP5_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 5_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0\
_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP6 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 6_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP6_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 6_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP6_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 6_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP6_3 __ADC_MODE none_ _AV\
G_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 6_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP7 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 7_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP7_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 7_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP7_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 7_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MA\
X 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP7_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 7_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP8 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 8_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP8_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 8_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP8_2 __ADC_MODE none_ \
_AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 8_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP8_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 8_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP9 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _IO_N none_ _IO_P none_ _SUPPLY_NUM 9_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP9_1 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 9_ _TH_HIGH 0_ _TH_LOW 0_ _TH\
_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP9_2 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 9_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP9_3 __ADC_MODE none_ _AVG_ENABLE 0_ _ENABLE 0_ _SUPPLY_NUM 9_ _TH_HIGH 0_ _TH_LOW 0_ _TH_MAX 0_ _TH_MIN 0_ _VOLTAGE none__ PMC_TAMPER_SUP_0_31_ENABLE 0 PMC_TAMPER_SUP_0_31_ENABLE_1 0 PMC_TAMPER_SUP_0_31_ENABLE_2 0 PMC_TAMPER_SUP_0_31_ENABLE_3 0 PMC_TAMPER_SUP_0_31_ERASE_BBRAM 0 PMC_TAMPER_SUP_0_31_ERASE_BBRAM_1 0\
 PMC_TAMPER_SUP_0_31_ERASE_BBRAM_2 0 PMC_TAMPER_SUP_0_31_ERASE_BBRAM_3 0 PMC_TAMPER_SUP_0_31_RESPONSE _SYS INTERRUPT_ PMC_TAMPER_SUP_0_31_RESPONSE_1 _SYS INTERRUPT_ PMC_TAMPER_SUP_0_31_RESPONSE_2 _SYS INTERRUPT_ PMC_TAMPER_SUP_0_31_RESPONSE_3 _SYS INTERRUPT_ PMC_TAMPER_TEMPERATURE_ENABLE 0 PMC_TAMPER_TEMPERATURE_ENABLE_1 0 PMC_TAMPER_TEMPERATURE_ENABLE_2 0 PMC_TAMPER_TEMPERATURE_ENABLE_3 0 PMC_TAMPER_TEMPERATURE_ERASE_BBRAM 0 PMC_TAMPER_TEMPERATURE_ERASE_BBRAM_1 0 PMC_TAMPER_TEMPERATURE_ERASE_BB\
RAM_2 0 PMC_TAMPER_TEMPERATURE_ERASE_BBRAM_3 0 PMC_TAMPER_TEMPERATURE_RESPONSE _SYS INTERRUPT_ PMC_TAMPER_TEMPERATURE_RESPONSE_1 _SYS INTERRUPT_ PMC_TAMPER_TEMPERATURE_RESPONSE_2 _SYS INTERRUPT_ PMC_TAMPER_TEMPERATURE_RESPONSE_3 _SYS INTERRUPT_ PMC_USE_CFU_SEU 0 PMC_USE_NOC_PMC_AXI0 0 PMC_USE_NOC_PMC_AXI1 0 PMC_USE_NOC_PMC_AXI2 0 PMC_USE_NOC_PMC_AXI3 0 PMC_USE_PL_ERR0 0 PMC_USE_PL_ERR1 0 PMC_USE_PL_ERR2 0 PMC_USE_PL_ERR3 0 PMC_USE_PL_PMC_AUX_REF_CLK 0 PMC_USE_PMC_NOC_AXI0 1 PMC_USE_PMC_NOC_AXI1 \
0 PMC_USE_PMC_NOC_AXI2 0 PMC_USE_PMC_NOC_AXI3 0 PMC_WDT_PERIOD 100 PMC_WDT_PERIPHERAL __ENABLE 0_ _IO _PMC_MIO 0___ POWER_REPORTING_MODE Custom PSPMC_MANUAL_CLK_ENABLE 0 PS_A72_ACTIVE_BLOCKS 2 PS_A72_LOAD 90 PS_BANK_2_IO_STANDARD LVCMOS1.8 PS_BANK_3_IO_STANDARD LVCMOS1.8 PS_BOARD_INTERFACE ps_pmc_fixed_io PS_CAN0_CLK __ENABLE 0_ _IO _PMC_MIO 0___ PS_CAN0_PERIPHERAL __ENABLE 0_ _IO _PMC_MIO 8 .. 9___ PS_CAN1_CLK __ENABLE 0_ _IO _PMC_MIO 0___ PS_CAN1_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 40 .. 41___\
 PS_CRF_ACPU_CTRL_ACT_FREQMHZ 1399.998657 PS_CRF_ACPU_CTRL_DIVISOR0 1 PS_CRF_ACPU_CTRL_FREQMHZ 1400 PS_CRF_ACPU_CTRL_SRCSEL APLL PS_CRF_APLL_CTRL_CLKOUTDIV 2 PS_CRF_APLL_CTRL_FBDIV 84 PS_CRF_APLL_CTRL_SRCSEL REF_CLK PS_CRF_APLL_TO_XPD_CTRL_DIVISOR0 4 PS_CRF_DBG_FPD_CTRL_ACT_FREQMHZ 399.999634 PS_CRF_DBG_FPD_CTRL_DIVISOR0 2 PS_CRF_DBG_FPD_CTRL_FREQMHZ 400 PS_CRF_DBG_FPD_CTRL_SRCSEL RPLL PS_CRF_DBG_TRACE_CTRL_ACT_FREQMHZ 300 PS_CRF_DBG_TRACE_CTRL_DIVISOR0 3 PS_CRF_DBG_TRACE_CTRL_FREQMHZ 300 PS_CRF\
_DBG_TRACE_CTRL_SRCSEL PPLL PS_CRF_FPD_LSBUS_CTRL_ACT_FREQMHZ 149.999863 PS_CRF_FPD_LSBUS_CTRL_DIVISOR0 4 PS_CRF_FPD_LSBUS_CTRL_FREQMHZ 150 PS_CRF_FPD_LSBUS_CTRL_SRCSEL PPLL PS_CRF_FPD_TOP_SWITCH_CTRL_ACT_FREQMHZ 799.999268 PS_CRF_FPD_TOP_SWITCH_CTRL_DIVISOR0 1 PS_CRF_FPD_TOP_SWITCH_CTRL_FREQMHZ 825 PS_CRF_FPD_TOP_SWITCH_CTRL_SRCSEL RPLL PS_CRL_CAN0_REF_CTRL_ACT_FREQMHZ 100 PS_CRL_CAN0_REF_CTRL_DIVISOR0 6 PS_CRL_CAN0_REF_CTRL_FREQMHZ 160 PS_CRL_CAN0_REF_CTRL_SRCSEL NPLL PS_CRL_CAN1_REF_CTRL_ACT_\
FREQMHZ 159.999847 PS_CRL_CAN1_REF_CTRL_DIVISOR0 5 PS_CRL_CAN1_REF_CTRL_FREQMHZ 160 PS_CRL_CAN1_REF_CTRL_SRCSEL RPLL PS_CRL_CPM_TOPSW_REF_CTRL_ACT_FREQMHZ 799.999268 PS_CRL_CPM_TOPSW_REF_CTRL_DIVISOR0 1 PS_CRL_CPM_TOPSW_REF_CTRL_FREQMHZ 825 PS_CRL_CPM_TOPSW_REF_CTRL_SRCSEL RPLL PS_CRL_CPU_R5_CTRL_ACT_FREQMHZ 599.999451 PS_CRL_CPU_R5_CTRL_DIVISOR0 1 PS_CRL_CPU_R5_CTRL_FREQMHZ 600 PS_CRL_CPU_R5_CTRL_SRCSEL PPLL PS_CRL_DBG_LPD_CTRL_ACT_FREQMHZ 399.999634 PS_CRL_DBG_LPD_CTRL_DIVISOR0 2 PS_CRL_DBG_LP\
D_CTRL_FREQMHZ 400 PS_CRL_DBG_LPD_CTRL_SRCSEL RPLL PS_CRL_DBG_TSTMP_CTRL_ACT_FREQMHZ 399.999634 PS_CRL_DBG_TSTMP_CTRL_DIVISOR0 2 PS_CRL_DBG_TSTMP_CTRL_FREQMHZ 400 PS_CRL_DBG_TSTMP_CTRL_SRCSEL RPLL PS_CRL_GEM0_REF_CTRL_ACT_FREQMHZ 124.999878 PS_CRL_GEM0_REF_CTRL_DIVISOR0 2 PS_CRL_GEM0_REF_CTRL_FREQMHZ 125 PS_CRL_GEM0_REF_CTRL_SRCSEL NPLL PS_CRL_GEM1_REF_CTRL_ACT_FREQMHZ 124.999878 PS_CRL_GEM1_REF_CTRL_DIVISOR0 2 PS_CRL_GEM1_REF_CTRL_FREQMHZ 125 PS_CRL_GEM1_REF_CTRL_SRCSEL NPLL PS_CRL_GEM_TSU_REF_\
CTRL_ACT_FREQMHZ 249.999756 PS_CRL_GEM_TSU_REF_CTRL_DIVISOR0 1 PS_CRL_GEM_TSU_REF_CTRL_FREQMHZ 250 PS_CRL_GEM_TSU_REF_CTRL_SRCSEL NPLL PS_CRL_I2C0_REF_CTRL_ACT_FREQMHZ 99.999908 PS_CRL_I2C0_REF_CTRL_DIVISOR0 6 PS_CRL_I2C0_REF_CTRL_FREQMHZ 100 PS_CRL_I2C0_REF_CTRL_SRCSEL PPLL PS_CRL_I2C1_REF_CTRL_ACT_FREQMHZ 99.999908 PS_CRL_I2C1_REF_CTRL_DIVISOR0 6 PS_CRL_I2C1_REF_CTRL_FREQMHZ 100 PS_CRL_I2C1_REF_CTRL_SRCSEL PPLL PS_CRL_IOU_SWITCH_CTRL_ACT_FREQMHZ 249.999756 PS_CRL_IOU_SWITCH_CTRL_DIVISOR0 1 PS_\
CRL_IOU_SWITCH_CTRL_FREQMHZ 250 PS_CRL_IOU_SWITCH_CTRL_SRCSEL NPLL PS_CRL_LPD_LSBUS_CTRL_ACT_FREQMHZ 149.999863 PS_CRL_LPD_LSBUS_CTRL_DIVISOR0 4 PS_CRL_LPD_LSBUS_CTRL_FREQMHZ 150 PS_CRL_LPD_LSBUS_CTRL_SRCSEL PPLL PS_CRL_LPD_TOP_SWITCH_CTRL_ACT_FREQMHZ 599.999451 PS_CRL_LPD_TOP_SWITCH_CTRL_DIVISOR0 1 PS_CRL_LPD_TOP_SWITCH_CTRL_FREQMHZ 600 PS_CRL_LPD_TOP_SWITCH_CTRL_SRCSEL PPLL PS_CRL_PSM_REF_CTRL_ACT_FREQMHZ 399.999634 PS_CRL_PSM_REF_CTRL_DIVISOR0 2 PS_CRL_PSM_REF_CTRL_FREQMHZ 400 PS_CRL_PSM_REF_\
CTRL_SRCSEL RPLL PS_CRL_RPLL_CTRL_CLKOUTDIV 4 PS_CRL_RPLL_CTRL_FBDIV 96 PS_CRL_RPLL_CTRL_SRCSEL REF_CLK PS_CRL_RPLL_TO_XPD_CTRL_DIVISOR0 1 PS_CRL_SPI0_REF_CTRL_ACT_FREQMHZ 200 PS_CRL_SPI0_REF_CTRL_DIVISOR0 6 PS_CRL_SPI0_REF_CTRL_FREQMHZ 200 PS_CRL_SPI0_REF_CTRL_SRCSEL PPLL PS_CRL_SPI1_REF_CTRL_ACT_FREQMHZ 200 PS_CRL_SPI1_REF_CTRL_DIVISOR0 6 PS_CRL_SPI1_REF_CTRL_FREQMHZ 200 PS_CRL_SPI1_REF_CTRL_SRCSEL PPLL PS_CRL_TIMESTAMP_REF_CTRL_ACT_FREQMHZ 99.999908 PS_CRL_TIMESTAMP_REF_CTRL_DIVISOR0 6 PS_CRL\
_TIMESTAMP_REF_CTRL_FREQMHZ 100 PS_CRL_TIMESTAMP_REF_CTRL_SRCSEL PPLL PS_CRL_UART0_REF_CTRL_ACT_FREQMHZ 99.999908 PS_CRL_UART0_REF_CTRL_DIVISOR0 6 PS_CRL_UART0_REF_CTRL_FREQMHZ 100 PS_CRL_UART0_REF_CTRL_SRCSEL PPLL PS_CRL_UART1_REF_CTRL_ACT_FREQMHZ 100 PS_CRL_UART1_REF_CTRL_DIVISOR0 12 PS_CRL_UART1_REF_CTRL_FREQMHZ 100 PS_CRL_UART1_REF_CTRL_SRCSEL PPLL PS_CRL_USB0_BUS_REF_CTRL_ACT_FREQMHZ 19.999981 PS_CRL_USB0_BUS_REF_CTRL_DIVISOR0 30 PS_CRL_USB0_BUS_REF_CTRL_FREQMHZ 20 PS_CRL_USB0_BUS_REF_CTRL_\
SRCSEL PPLL PS_CRL_USB3_DUAL_REF_CTRL_ACT_FREQMHZ 20 PS_CRL_USB3_DUAL_REF_CTRL_DIVISOR0 60 PS_CRL_USB3_DUAL_REF_CTRL_FREQMHZ 10 PS_CRL_USB3_DUAL_REF_CTRL_SRCSEL PPLL PS_DDRC_ENABLE 1 PS_DDR_RAM_HIGHADDR_OFFSET 0x800000000 PS_DDR_RAM_LOWADDR_OFFSET 0x80000000 PS_ENET0_MDIO __ENABLE 1_ _IO _PS_MIO 24 .. 25___ PS_ENET0_PERIPHERAL __ENABLE 1_ _IO _PS_MIO 0 .. 11___ PS_ENET1_MDIO __ENABLE 0_ _IO _PMC_MIO 50 .. 51___ PS_ENET1_PERIPHERAL __ENABLE 1_ _IO _PS_MIO 12 .. 23___ PS_EN_AXI_STATUS_PORTS 0 PS_E\
N_PORTS_CONTROLLER_BASED 0 PS_EXPAND_CORESIGHT 0 PS_EXPAND_FPD_SLAVES 0 PS_EXPAND_GIC 0 PS_EXPAND_LPD_SLAVES 0 PS_FPD_INTERCONNECT_LOAD 90 PS_FTM_CTI_IN0 0 PS_FTM_CTI_IN1 0 PS_FTM_CTI_IN2 0 PS_FTM_CTI_IN3 0 PS_FTM_CTI_OUT0 0 PS_FTM_CTI_OUT1 0 PS_FTM_CTI_OUT2 0 PS_FTM_CTI_OUT3 0 PS_GEM0_COHERENCY 0 PS_GEM0_ROUTE_THROUGH_FPD 0 PS_GEM0_TSU_INC_CTRL 3 PS_GEM1_COHERENCY 0 PS_GEM1_ROUTE_THROUGH_FPD 0 PS_GEM_TSU __ENABLE 0_ _IO _PS_MIO 24___ PS_GEM_TSU_CLK_PORT_PAIR 0 PS_GEN_IPI0_ENABLE 1 PS_GEN_IPI0_M\
ASTER A72 PS_GEN_IPI1_ENABLE 1 PS_GEN_IPI1_MASTER A72 PS_GEN_IPI2_ENABLE 1 PS_GEN_IPI2_MASTER A72 PS_GEN_IPI3_ENABLE 1 PS_GEN_IPI3_MASTER A72 PS_GEN_IPI4_ENABLE 1 PS_GEN_IPI4_MASTER A72 PS_GEN_IPI5_ENABLE 1 PS_GEN_IPI5_MASTER A72 PS_GEN_IPI6_ENABLE 1 PS_GEN_IPI6_MASTER A72 PS_GEN_IPI_PMCNOBUF_ENABLE 1 PS_GEN_IPI_PMCNOBUF_MASTER PMC PS_GEN_IPI_PMC_ENABLE 1 PS_GEN_IPI_PMC_MASTER PMC PS_GEN_IPI_PSM_ENABLE 1 PS_GEN_IPI_PSM_MASTER PSM PS_GPIO2_MIO_PERIPHERAL __ENABLE 0_ _IO _PS_MIO 0 .. 25___ PS_GPIO\
_EMIO_PERIPHERAL_ENABLE 0 PS_GPIO_EMIO_WIDTH 32 PS_HSDP0_REFCLK 0 PS_HSDP1_REFCLK 0 PS_HSDP_EGRESS_TRAFFIC JTAG PS_HSDP_INGRESS_TRAFFIC JTAG PS_HSDP_MODE NONE PS_HSDP_SAME_EGRESS_AS_INGRESS_TRAFFIC 1 PS_I2C0_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 46 .. 47___ PS_I2C1_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 44 .. 45___ PS_I2CSYSMON_PERIPHERAL __ENABLE 0_ _IO _PS_MIO 23 .. 24___ PS_IRQ_USAGE __CH0 0_ _CH1 0_ _CH10 0_ _CH11 0_ _CH12 0_ _CH13 0_ _CH14 0_ _CH15 0_ _CH2 0_ _CH3 0_ _CH4 0_ _CH5 0_ _CH6 0_ _CH7\
 0_ _CH8 0_ _CH9 0__ PS_KAT_ENABLE 1 PS_KAT_ENABLE_1 1 PS_KAT_ENABLE_2 1 PS_KAT_ENABLE_3 1 PS_LPDMA0_COHERENCY 0 PS_LPDMA0_ROUTE_THROUGH_FPD 0 PS_LPDMA1_COHERENCY 0 PS_LPDMA1_ROUTE_THROUGH_FPD 0 PS_LPDMA2_COHERENCY 0 PS_LPDMA2_ROUTE_THROUGH_FPD 0 PS_LPDMA3_COHERENCY 0 PS_LPDMA3_ROUTE_THROUGH_FPD 0 PS_LPDMA4_COHERENCY 0 PS_LPDMA4_ROUTE_THROUGH_FPD 0 PS_LPDMA5_COHERENCY 0 PS_LPDMA5_ROUTE_THROUGH_FPD 0 PS_LPDMA6_COHERENCY 0 PS_LPDMA6_ROUTE_THROUGH_FPD 0 PS_LPDMA7_COHERENCY 0 PS_LPDMA7_ROUTE_THROUGH\
_FPD 0 PS_LPD_DMA_CHANNEL_ENABLE __CH0 0_ _CH1 0_ _CH2 0_ _CH3 0_ _CH4 0_ _CH5 0_ _CH6 0_ _CH7 0__ PS_LPD_DMA_CH_TZ __CH0 NonSecure_ _CH1 NonSecure_ _CH2 NonSecure_ _CH3 NonSecure_ _CH4 NonSecure_ _CH5 NonSecure_ _CH6 NonSecure_ _CH7 NonSecure__ PS_LPD_DMA_ENABLE 0 PS_LPD_INTERCONNECT_LOAD 90 PS_MIO0 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PS_MIO1 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA d\
efault_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PS_MIO10 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO11 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO12 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PS_MIO13 __AUX_IO 0_ _DIRECTIO\
N out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PS_MIO14 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PS_MIO15 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PS_MIO16 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USA\
GE Reserved__ PS_MIO17 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PS_MIO18 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO19 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL disable_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO2 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ \
_PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PS_MIO20 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO21 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL disable_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO22 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO23 __AUX_IO 0_ _DIRECTION in_ _D\
RIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO24 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PS_MIO25 __AUX_IO 0_ _DIRECTION inout_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO3 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reser\
ved__ PS_MIO4 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PS_MIO5 __AUX_IO 0_ _DIRECTION out_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 1_ _SLEW slow_ _USAGE Reserved__ PS_MIO6 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO7 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL disabl\
e_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO8 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL pullup_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_MIO9 __AUX_IO 0_ _DIRECTION in_ _DRIVE_STRENGTH 8mA_ _OUTPUT_DATA default_ _PULL disable_ _SCHMITT 0_ _SLEW slow_ _USAGE Reserved__ PS_M_AXI_FPD_DATA_WIDTH 128 PS_M_AXI_GP4_DATA_WIDTH 128 PS_M_AXI_LPD_DATA_WIDTH 128 PS_NOC_PS_CCI_DATA_WIDTH 128 PS_NOC_PS_NCI_DATA_WIDTH 128 PS_NOC_PS_PCI_DATA_WIDTH 128 PS_NOC_PS_PMC_D\
ATA_WIDTH 128 PS_NUM_F2P0_INTR_INPUTS 1 PS_NUM_F2P1_INTR_INPUTS 1 PS_NUM_FABRIC_RESETS 1 PS_OCM_ACTIVE_BLOCKS 1 PS_PCIE1_PERIPHERAL_ENABLE 0 PS_PCIE2_PERIPHERAL_ENABLE 0 PS_PCIE_EP_RESET1_IO _PMC_MIO 38_ PS_PCIE_EP_RESET2_IO _PMC_MIO 39_ PS_PCIE_PERIPHERAL_ENABLE 0 PS_PCIE_RESET _ENABLE 1_ PS_PCIE_ROOT_RESET1_IO None PS_PCIE_ROOT_RESET1_IO_DIR output PS_PCIE_ROOT_RESET1_POLARITY _Active Low_ PS_PCIE_ROOT_RESET2_IO None PS_PCIE_ROOT_RESET2_IO_DIR output PS_PCIE_ROOT_RESET2_POLARITY _Active Low_ P\
S_PL_CONNECTIVITY_MODE Custom PS_PL_DONE 0 PS_PL_PASS_AXPROT_VALUE 0 PS_PMCPL_CLK0_BUF 1 PS_PMCPL_CLK1_BUF 1 PS_PMCPL_CLK2_BUF 1 PS_PMCPL_CLK3_BUF 1 PS_PMCPL_IRO_CLK_BUF 1 PS_PMU_PERIPHERAL_ENABLE 0 PS_PS_ENABLE 0 PS_PS_NOC_CCI_DATA_WIDTH 128 PS_PS_NOC_NCI_DATA_WIDTH 128 PS_PS_NOC_PCI_DATA_WIDTH 128 PS_PS_NOC_PMC_DATA_WIDTH 128 PS_PS_NOC_RPU_DATA_WIDTH 128 PS_R5_ACTIVE_BLOCKS 2 PS_R5_LOAD 90 PS_RED_KEY_CLEAR_ENABLE 0 PS_RED_KEY_CLEAR_ENABLE_1 0 PS_RED_KEY_CLEAR_ENABLE_2 0 PS_RED_KEY_CLEAR_ENABLE\
_3 0 PS_RPU_COHERENCY 0 PS_SLR_TYPE master PS_SMON_PL_PORTS_ENABLE 0 PS_SPI0 __GRP_SS0_ENABLE 0_ _GRP_SS0_IO _PMC_MIO 15__ _GRP_SS1_ENABLE 0_ _GRP_SS1_IO _PMC_MIO 14__ _GRP_SS2_ENABLE 0_ _GRP_SS2_IO _PMC_MIO 13__ _PERIPHERAL_ENABLE 0_ _PERIPHERAL_IO _PMC_MIO 12 .. 17___ PS_SPI1 __GRP_SS0_ENABLE 0_ _GRP_SS0_IO _PS_MIO 9__ _GRP_SS1_ENABLE 0_ _GRP_SS1_IO _PS_MIO 8__ _GRP_SS2_ENABLE 0_ _GRP_SS2_IO _PS_MIO 7__ _PERIPHERAL_ENABLE 0_ _PERIPHERAL_IO _PS_MIO 6 .. 11___ PS_S_AXI_ACE_DATA_WIDTH 128 PS_S_AX\
I_ACP_DATA_WIDTH 128 PS_S_AXI_FPD_DATA_WIDTH 128 PS_S_AXI_GP2_DATA_WIDTH 128 PS_S_AXI_LPD_DATA_WIDTH 128 PS_TCM_ACTIVE_BLOCKS 2 PS_TIE_MJTAG_TCK_TO_GND 1 PS_TRACE_PERIPHERAL __ENABLE 0_ _IO _PMC_MIO 30 .. 47___ PS_TRACE_WIDTH 2Bit PS_TRISTATE_INVERTED 1 PS_TTC0_CLK __ENABLE 0_ _IO _PS_MIO 6___ PS_TTC0_PERIPHERAL_ENABLE 0 PS_TTC0_REF_CTRL_ACT_FREQMHZ 50 PS_TTC0_REF_CTRL_FREQMHZ 50 PS_TTC0_WAVEOUT __ENABLE 0_ _IO _PS_MIO 7___ PS_TTC1_CLK __ENABLE 0_ _IO _PS_MIO 12___ PS_TTC1_PERIPHERAL_ENABLE 0 PS\
_TTC1_REF_CTRL_ACT_FREQMHZ 50 PS_TTC1_REF_CTRL_FREQMHZ 50 PS_TTC1_WAVEOUT __ENABLE 0_ _IO _PS_MIO 13___ PS_TTC2_CLK __ENABLE 0_ _IO _PS_MIO 2___ PS_TTC2_PERIPHERAL_ENABLE 0 PS_TTC2_REF_CTRL_ACT_FREQMHZ 50 PS_TTC2_REF_CTRL_FREQMHZ 50 PS_TTC2_WAVEOUT __ENABLE 0_ _IO _PS_MIO 3___ PS_TTC3_CLK __ENABLE 0_ _IO _PS_MIO 16___ PS_TTC3_PERIPHERAL_ENABLE 0 PS_TTC3_REF_CTRL_ACT_FREQMHZ 50 PS_TTC3_REF_CTRL_FREQMHZ 50 PS_TTC3_WAVEOUT __ENABLE 0_ _IO _PS_MIO 17___ PS_TTC_APB_CLK_TTC0_SEL APB PS_TTC_APB_CLK_TTC\
1_SEL APB PS_TTC_APB_CLK_TTC2_SEL APB PS_TTC_APB_CLK_TTC3_SEL APB PS_UART0_BAUD_RATE 115200 PS_UART0_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 42 .. 43___ PS_UART0_RTS_CTS __ENABLE 0_ _IO _PS_MIO 2 .. 3___ PS_UART1_BAUD_RATE 115200 PS_UART1_PERIPHERAL __ENABLE 0_ _IO _PMC_MIO 4 .. 5___ PS_UART1_RTS_CTS __ENABLE 0_ _IO _PMC_MIO 6 .. 7___ PS_UNITS_MODE Custom PS_USB3_PERIPHERAL __ENABLE 1_ _IO _PMC_MIO 13 .. 25___ PS_USB_COHERENCY 0 PS_USB_ROUTE_THROUGH_FPD 0 PS_USE_ACE_LITE 0 PS_USE_APU_EVENT_BUS 0 PS_\
USE_APU_INTERRUPT 0 PS_USE_AXI4_EXT_USER_BITS 0 PS_USE_BSCAN_USER1 0 PS_USE_BSCAN_USER2 0 PS_USE_BSCAN_USER3 0 PS_USE_BSCAN_USER4 0 PS_USE_CAPTURE 0 PS_USE_CLK 0 PS_USE_DEBUG_TEST 0 PS_USE_DIFF_RW_CLK_S_AXI_FPD 0 PS_USE_DIFF_RW_CLK_S_AXI_GP2 0 PS_USE_DIFF_RW_CLK_S_AXI_LPD 0 PS_USE_ENET0_PTP 0 PS_USE_ENET1_PTP 0 PS_USE_FIFO_ENET0 0 PS_USE_FIFO_ENET1 0 PS_USE_FIXED_IO 0 PS_USE_FPD_AXI_NOC0 0 PS_USE_FPD_AXI_NOC1 0 PS_USE_FPD_CCI_NOC 1 PS_USE_FPD_CCI_NOC0 1 PS_USE_FPD_CCI_NOC1 0 PS_USE_FPD_CCI_NOC2 \
0 PS_USE_FPD_CCI_NOC3 0 PS_USE_FTM_GPI 0 PS_USE_FTM_GPO 0 PS_USE_HSDP_PL 0 PS_USE_MJTAG_TCK_TIE_OFF 0 PS_USE_M_AXI_FPD 0 PS_USE_M_AXI_LPD 0 PS_USE_NOC_FPD_AXI0 1 PS_USE_NOC_FPD_AXI1 0 PS_USE_NOC_FPD_CCI0 0 PS_USE_NOC_FPD_CCI1 0 PS_USE_NOC_LPD_AXI0 1 PS_USE_NOC_PS_PCI_0 0 PS_USE_NOC_PS_PMC_0 0 PS_USE_NPI_CLK 0 PS_USE_NPI_RST 0 PS_USE_PL_FPD_AUX_REF_CLK 0 PS_USE_PL_LPD_AUX_REF_CLK 0 PS_USE_PMC 0 PS_USE_PMCPL_CLK0 1 PS_USE_PMCPL_CLK1 0 PS_USE_PMCPL_CLK2 0 PS_USE_PMCPL_CLK3 0 PS_USE_PMCPL_IRO_CLK 0 \
PS_USE_PSPL_IRQ_FPD 0 PS_USE_PSPL_IRQ_LPD 0 PS_USE_PSPL_IRQ_PMC 0 PS_USE_PS_NOC_PCI_0 0 PS_USE_PS_NOC_PCI_1 0 PS_USE_PS_NOC_PMC_0 0 PS_USE_PS_NOC_PMC_1 0 PS_USE_RPU_EVENT 0 PS_USE_RPU_INTERRUPT 0 PS_USE_RTC 0 PS_USE_SMMU 0 PS_USE_STARTUP 0 PS_USE_STM 0 PS_USE_S_ACP_FPD 0 PS_USE_S_AXI_ACE 0 PS_USE_S_AXI_FPD 0 PS_USE_S_AXI_GP2 0 PS_USE_S_AXI_LPD 0 PS_USE_TRACE_ATB 0 PS_WDT0_REF_CTRL_ACT_FREQMHZ 100 PS_WDT0_REF_CTRL_FREQMHZ 100 PS_WDT0_REF_CTRL_SEL NONE PS_WDT1_REF_CTRL_ACT_FREQMHZ 100 PS_WDT1_REF_\
CTRL_FREQMHZ 100 PS_WDT1_REF_CTRL_SEL NONE PS_WWDT0_CLK __ENABLE 0_ _IO _PMC_MIO 0___ PS_WWDT0_PERIPHERAL __ENABLE 0_ _IO _PMC_MIO 0 .. 5___ PS_WWDT1_CLK __ENABLE 0_ _IO _PMC_MIO 6___ PS_WWDT1_PERIPHERAL __ENABLE 0_ _IO _PMC_MIO 6 .. 11___ SEM_ERROR_HANDLE_OPTIONS _Detect & Correct_ SEM_EVENT_LOG_OPTIONS _Log & Notify_ SEM_MEM_BUILT_IN_SELF_TEST 0 SEM_MEM_ENABLE_ALL_TEST_FEATURE 0 SEM_MEM_ENABLE_SCAN_AFTER _Immediate Start_ SEM_MEM_GOLDEN_ECC 0 SEM_MEM_GOLDEN_ECC_SW 0 SEM_MEM_SCAN 0 SEM_NPI_BUIL\
T_IN_SELF_TEST 0 SEM_NPI_ENABLE_ALL_TEST_FEATURE 0 SEM_NPI_ENABLE_SCAN_AFTER _Immediate Start_ SEM_NPI_GOLDEN_CHECKSUM_SW 0 SEM_NPI_SCAN 0 SEM_TIME_INTERVAL_BETWEEN_SCANS 80 SLR1_PMC_CRP_HSM0_REF_CTRL_ACT_FREQMHZ 99.999 SLR1_PMC_CRP_HSM0_REF_CTRL_DIVISOR0 12 SLR1_PMC_CRP_HSM0_REF_CTRL_FREQMHZ 33.333 SLR1_PMC_CRP_HSM0_REF_CTRL_SRCSEL PPLL SLR1_PMC_CRP_HSM1_REF_CTRL_ACT_FREQMHZ 33.33 SLR1_PMC_CRP_HSM1_REF_CTRL_DIVISOR0 36 SLR1_PMC_CRP_HSM1_REF_CTRL_FREQMHZ 33.333 SLR1_PMC_CRP_HSM1_REF_CTRL_SRCSEL \
PPLL SLR1_PMC_HSM0_CLK_ENABLE 1 SLR1_PMC_HSM0_CLK_OUT_ENABLE 0 SLR1_PMC_HSM1_CLK_ENABLE 1 SLR1_PMC_HSM1_CLK_OUT_ENABLE 0 SLR1_PS_USE_CAPTURE 0 SLR2_PMC_CRP_HSM0_REF_CTRL_ACT_FREQMHZ 99.999 SLR2_PMC_CRP_HSM0_REF_CTRL_DIVISOR0 12 SLR2_PMC_CRP_HSM0_REF_CTRL_FREQMHZ 33.333 SLR2_PMC_CRP_HSM0_REF_CTRL_SRCSEL PPLL SLR2_PMC_CRP_HSM1_REF_CTRL_ACT_FREQMHZ 33.33 SLR2_PMC_CRP_HSM1_REF_CTRL_DIVISOR0 36 SLR2_PMC_CRP_HSM1_REF_CTRL_FREQMHZ 33.333 SLR2_PMC_CRP_HSM1_REF_CTRL_SRCSEL PPLL SLR2_PMC_HSM0_CLK_ENABLE 1\
 SLR2_PMC_HSM0_CLK_OUT_ENABLE 0 SLR2_PMC_HSM1_CLK_ENABLE 1 SLR2_PMC_HSM1_CLK_OUT_ENABLE 0 SLR2_PS_USE_CAPTURE 0 SLR3_PMC_CRP_HSM0_REF_CTRL_ACT_FREQMHZ 99.999 SLR3_PMC_CRP_HSM0_REF_CTRL_DIVISOR0 12 SLR3_PMC_CRP_HSM0_REF_CTRL_FREQMHZ 33.333 SLR3_PMC_CRP_HSM0_REF_CTRL_SRCSEL PPLL SLR3_PMC_CRP_HSM1_REF_CTRL_ACT_FREQMHZ 33.33 SLR3_PMC_CRP_HSM1_REF_CTRL_DIVISOR0 36 SLR3_PMC_CRP_HSM1_REF_CTRL_FREQMHZ 33.333 SLR3_PMC_CRP_HSM1_REF_CTRL_SRCSEL PPLL SLR3_PMC_HSM0_CLK_ENABLE 1 SLR3_PMC_HSM0_CLK_OUT_ENABLE 0\
 SLR3_PMC_HSM1_CLK_ENABLE 1 SLR3_PMC_HSM1_CLK_OUT_ENABLE 0 SLR3_PS_USE_CAPTURE 0 SMON_ALARMS Set_Alarms_On SMON_ENABLE_INT_VOLTAGE_MONITORING 0 SMON_ENABLE_TEMP_AVERAGING 0 SMON_HI_PERF_MODE 1 SMON_INTERFACE_TO_USE None SMON_INT_MEASUREMENT_ALARM_ENABLE 0 SMON_INT_MEASUREMENT_AVG_ENABLE 0 SMON_INT_MEASUREMENT_ENABLE 0 SMON_INT_MEASUREMENT_MODE 0 SMON_INT_MEASUREMENT_TH_HIGH 0 SMON_INT_MEASUREMENT_TH_LOW 0 SMON_MEAS0 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0\
_ _MODE _2 V unipolar__ _NAME GTY_AVCCAUX_103_ _SUPPLY_NUM 0__ SMON_MEAS1 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCCAUX_104_ _SUPPLY_NUM 0__ SMON_MEAS10 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCCAUX_206_ _SUPPLY_NUM 0__ SMON_MEAS100 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_10\
3_ _SUPPLY_NUM 0__ SMON_MEAS101 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS102 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS103 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS104 __ALARM_ENABLE 0_ _ALARM_LO\
WER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS105 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS106 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS107 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MOD\
E None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS108 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS109 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS11 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCC_103_ _SUPPLY_NUM 0__ SMON_M\
EAS110 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS111 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS112 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS113 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.\
00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS114 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS115 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS116 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PK\
G_103_ _SUPPLY_NUM 0__ SMON_MEAS117 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS118 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS119 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS12 __ALARM_ENABLE 0_ _ALARM\
_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCC_104_ _SUPPLY_NUM 0__ SMON_MEAS120 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS121 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS122 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABL\
E 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS123 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS124 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS125 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SM\
ON_MEAS126 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS127 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS128 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS129 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPE\
R 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS13 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCC_105_ _SUPPLY_NUM 0__ SMON_MEAS130 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS131 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT\
_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS132 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS133 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS134 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS135 __ALARM_ENABLE\
 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS136 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS137 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS138 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _E\
NABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS139 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS14 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCC_106_ _SUPPLY_NUM 0__ SMON_MEAS140 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_N\
UM 0__ SMON_MEAS141 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS142 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS143 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS144 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _A\
LARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS145 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS146 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS147 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAM\
E GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS148 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS149 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS15 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCC_200_ _SUPPLY_NUM 0__ SMON_MEAS150 __ALA\
RM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS151 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS152 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS153 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE\
_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS154 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS155 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS156 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPP\
LY_NUM 0__ SMON_MEAS157 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS158 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS159 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS16 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_\
 _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCC_201_ _SUPPLY_NUM 0__ SMON_MEAS160 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103__ SMON_MEAS161 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103__ SMON_MEAS162 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCINT__ \
SMON_MEAS163 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCAUX__ SMON_MEAS164 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCC_RAM__ SMON_MEAS165 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCC_SOC__ SMON_MEAS166 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _\
2 V unipolar__ _NAME VCC_PSFP__ SMON_MEAS167 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCC_PSLP__ SMON_MEAS168 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCAUX_PMC__ SMON_MEAS169 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCC_PMC__ SMON_MEAS17 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.0\
0_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCC_202_ _SUPPLY_NUM 0__ SMON_MEAS170 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103__ SMON_MEAS171 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103__ SMON_MEAS172 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103__ SMON_MEAS173 __AL\
ARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103__ SMON_MEAS174 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103__ SMON_MEAS175 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103__ SMON_MEAS18 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME\
 GTY_AVCC_203_ _SUPPLY_NUM 0__ SMON_MEAS19 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCC_204_ _SUPPLY_NUM 0__ SMON_MEAS2 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCCAUX_105_ _SUPPLY_NUM 0__ SMON_MEAS20 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCC_205_ _SUPPLY_NUM 0__ SMON_MEAS21\
 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCC_206_ _SUPPLY_NUM 0__ SMON_MEAS22 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVTT_103_ _SUPPLY_NUM 0__ SMON_MEAS23 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVTT_104_ _SUPPLY_NUM 0__ SMON_MEAS24 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM\
_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVTT_105_ _SUPPLY_NUM 0__ SMON_MEAS25 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVTT_106_ _SUPPLY_NUM 0__ SMON_MEAS26 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVTT_200_ _SUPPLY_NUM 0__ SMON_MEAS27 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE\
 _2 V unipolar__ _NAME GTY_AVTT_201_ _SUPPLY_NUM 0__ SMON_MEAS28 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVTT_202_ _SUPPLY_NUM 0__ SMON_MEAS29 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVTT_203_ _SUPPLY_NUM 0__ SMON_MEAS3 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCCAUX_106_ _SUPP\
LY_NUM 0__ SMON_MEAS30 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVTT_204_ _SUPPLY_NUM 0__ SMON_MEAS31 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVTT_205_ _SUPPLY_NUM 0__ SMON_MEAS32 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVTT_206_ _SUPPLY_NUM 0__ SMON_MEAS33 __ALARM_ENABLE 0_ _AL\
ARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCAUX_ _SUPPLY_NUM 0__ SMON_MEAS34 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCAUX_PMC_ _SUPPLY_NUM 0__ SMON_MEAS35 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCAUX_SMON_ _SUPPLY_NUM 0__ SMON_MEAS36 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _EN\
ABLE 0_ _MODE _2 V unipolar__ _NAME VCCINT_ _SUPPLY_NUM 0__ SMON_MEAS37 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 4.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _4 V unipolar__ _NAME VCCO_306_ _SUPPLY_NUM 0__ SMON_MEAS38 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 4.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _4 V unipolar__ _NAME VCCO_406_ _SUPPLY_NUM 0__ SMON_MEAS39 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 4.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _4 V unipolar__ _NAME VCCO_500_ _SUPPLY_NUM \
0__ SMON_MEAS4 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCCAUX_200_ _SUPPLY_NUM 0__ SMON_MEAS40 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 4.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _4 V unipolar__ _NAME VCCO_501_ _SUPPLY_NUM 0__ SMON_MEAS41 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 4.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _4 V unipolar__ _NAME VCCO_502_ _SUPPLY_NUM 0__ SMON_MEAS42 __ALARM_ENABLE 0_ _ALARM_LOWER 0.0\
0_ _ALARM_UPPER 4.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _4 V unipolar__ _NAME VCCO_503_ _SUPPLY_NUM 0__ SMON_MEAS43 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCO_700_ _SUPPLY_NUM 0__ SMON_MEAS44 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCO_701_ _SUPPLY_NUM 0__ SMON_MEAS45 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2\
 V unipolar__ _NAME VCCO_702_ _SUPPLY_NUM 0__ SMON_MEAS46 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCO_703_ _SUPPLY_NUM 0__ SMON_MEAS47 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCO_704_ _SUPPLY_NUM 0__ SMON_MEAS48 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCO_705_ _SUPPLY_NUM 0__ SMON_MEAS4\
9 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCO_706_ _SUPPLY_NUM 0__ SMON_MEAS5 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCCAUX_201_ _SUPPLY_NUM 0__ SMON_MEAS50 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCO_707_ _SUPPLY_NUM 0__ SMON_MEAS51 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPE\
R 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCO_708_ _SUPPLY_NUM 0__ SMON_MEAS52 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCO_709_ _SUPPLY_NUM 0__ SMON_MEAS53 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCCO_710_ _SUPPLY_NUM 0__ SMON_MEAS54 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ \
_NAME VCCO_711_ _SUPPLY_NUM 0__ SMON_MEAS55 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCC_BATT_ _SUPPLY_NUM 0__ SMON_MEAS56 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCC_PMC_ _SUPPLY_NUM 0__ SMON_MEAS57 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCC_PSFP_ _SUPPLY_NUM 0__ SMON_MEAS58 __ALARM_ENABL\
E 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCC_PSLP_ _SUPPLY_NUM 0__ SMON_MEAS59 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCC_RAM_ _SUPPLY_NUM 0__ SMON_MEAS6 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCCAUX_202_ _SUPPLY_NUM 0__ SMON_MEAS60 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE\
_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME VCC_SOC_ _SUPPLY_NUM 0__ SMON_MEAS61 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 1.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _1 V unipolar__ _NAME VP_VN_ _SUPPLY_NUM 0__ SMON_MEAS62 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS63 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_\
NUM 0__ SMON_MEAS64 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS65 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS66 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS67 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALAR\
M_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS68 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS69 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS7 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _\
NAME GTY_AVCCAUX_203_ _SUPPLY_NUM 0__ SMON_MEAS70 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS71 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS72 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS73 __ALARM_ENAB\
LE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS74 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS75 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS76 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _EN\
ABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS77 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS78 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS79 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SM\
ON_MEAS8 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCCAUX_204_ _SUPPLY_NUM 0__ SMON_MEAS80 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS81 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS82 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_\
UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS83 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS84 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS85 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVA\
UX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS86 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS87 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS88 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS89 __ALARM_ENABLE 0_ _ALA\
RM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS9 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE _2 V unipolar__ _NAME GTY_AVCCAUX_205_ _SUPPLY_NUM 0__ SMON_MEAS90 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS91 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENAB\
LE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS92 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS93 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS94 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON\
_MEAS95 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS96 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS97 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS98 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00\
_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEAS99 __ALARM_ENABLE 0_ _ALARM_LOWER 0.00_ _ALARM_UPPER 2.00_ _AVERAGE_EN 0_ _ENABLE 0_ _MODE None_ _NAME GT_AVAUX_PKG_103_ _SUPPLY_NUM 0__ SMON_MEASUREMENT_COUNT 62 SMON_MEASUREMENT_LIST BANK_VOLTAGE_GTY_AVTT-GTY_AVTT_103_GTY_AVTT_104_GTY_AVTT_105_GTY_AVTT_106_GTY_AVTT_200_GTY_AVTT_201_GTY_AVTT_202_GTY_AVTT_203_GTY_AVTT_204_GTY_AVTT_205_GTY_AVTT_206#VCC-GTY_AVCC_103_GTY_AVCC_104_GTY_AVCC_105_GTY_AVCC_106_GTY_A\
VCC_200_GTY_AVCC_201_GTY_AVCC_202_GTY_AVCC_203_GTY_AVCC_204_GTY_AVCC_205_GTY_AVCC_206#VCCAUX-GTY_AVCCAUX_103_GTY_AVCCAUX_104_GTY_AVCCAUX_105_GTY_AVCCAUX_106_GTY_AVCCAUX_200_GTY_AVCCAUX_201_GTY_AVCCAUX_202_GTY_AVCCAUX_203_GTY_AVCCAUX_204_GTY_AVCCAUX_205_GTY_AVCCAUX_206#VCCO-VCCO_306_VCCO_406_VCCO_500_VCCO_501_VCCO_502_VCCO_503_VCCO_700_VCCO_701_VCCO_702_VCCO_703_VCCO_704_VCCO_705_VCCO_706_VCCO_707_VCCO_708_VCCO_709_VCCO_710_VCCO_711|DEDICATED_PAD_VP-VP_VN|SUPPLY_VOLTAGE_VCC-VCC_BATT_VCC_PMC_VCC_P\
SFP_VCC_PSLP_VCC_RAM_VCC_SOC#VCCAUX-VCCAUX_VCCAUX_PMC_VCCAUX_SMON#VCCINT-VCCINT SMON_MUX_ADDR_ENABLE 0 SMON_OT __THRESHOLD_LOWER 70_ _THRESHOLD_UPPER 125__ SMON_PMBUS_ADDRESS 0x0 SMON_PMBUS_UNRESTRICTED 0 SMON_REFERENCE_SOURCE Internal SMON_TEMP_AVERAGING_SAMPLES 0 SMON_TEMP_THRESHOLD 0 SMON_USER_TEMP __THRESHOLD_LOWER 70_ _THRESHOLD_UPPER 125_ _USER_ALARM_TYPE hysteresis__ SMON_VAUX_CH0 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO\
0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH0_ _SUPPLY_NUM 0__ SMON_VAUX_CH1 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH1_ _SUPPLY_NUM 0__ SMON_VAUX_CH10 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH10_ _SUPPLY_NUM 0__ SMON_VAUX_CH11 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVE\
RAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH11_ _SUPPLY_NUM 0__ SMON_VAUX_CH12 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH12_ _SUPPLY_NUM 0__ SMON_VAUX_CH13 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH13_ _SUPPLY_NUM 0__ SMON_VAUX_C\
H14 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH14_ _SUPPLY_NUM 0__ SMON_VAUX_CH15 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH15_ _SUPPLY_NUM 0__ SMON_VAUX_CH2 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 \
V unipolar__ _NAME VAUX_CH2_ _SUPPLY_NUM 0__ SMON_VAUX_CH3 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH3_ _SUPPLY_NUM 0__ SMON_VAUX_CH4 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH4_ _SUPPLY_NUM 0__ SMON_VAUX_CH5 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE \
0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH5_ _SUPPLY_NUM 0__ SMON_VAUX_CH6 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH6_ _SUPPLY_NUM 0__ SMON_VAUX_CH7 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH7_ _SUPPLY_NUM 0__ SMON_VAUX_CH8 __ALARM_ENABLE 0_ _AL\
ARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH8_ _SUPPLY_NUM 0__ SMON_VAUX_CH9 __ALARM_ENABLE 0_ _ALARM_LOWER 0_ _ALARM_UPPER 1_ _AVERAGE_EN 0_ _ENABLE 0_ _IO_N PMC_MIO1_500_ _IO_P PMC_MIO0_500_ _MODE _1 V unipolar__ _NAME VAUX_CH9_ _SUPPLY_NUM 0__ SMON_VAUX_IO_BANK MIO_BANK0 SMON_VOLTAGE_AVERAGING_SAMPLES None SPP_PSPMC_FROM_CORE_WIDTH 12000 SPP_PSPMC_TO_CORE_WIDTH 12000 SUBPRESET1 Custom USE_UART0_IN_DEVICE_BOO\
T 0 preset None,PS_PMC_CONFIG_APPLIED=1,CPM_CONFIG=CPM_PCIE0_MODES None,CPM_CONFIG_INTERNAL=AURORA_LINE_RATE_GPBS 10.0 BOOT_SECONDARY_PCIE_ENABLE 0 CPM_A0_REFCLK 0 CPM_A1_REFCLK 0 CPM_AUX0_REF_CTRL_ACT_FREQMHZ 899.991028 CPM_AUX0_REF_CTRL_DIVISOR0 2 CPM_AUX0_REF_CTRL_FREQMHZ 900 CPM_AUX1_REF_CTRL_ACT_FREQMHZ 899.991028 CPM_AUX1_REF_CTRL_DIVISOR0 2 CPM_AUX1_REF_CTRL_FREQMHZ 900 CPM_AXI_SLV_BRIDGE_BASE_ADDRR_H 0x00000006 CPM_AXI_SLV_BRIDGE_BASE_ADDRR_L 0x00000000 CPM_AXI_SLV_MULTQ_BASE_ADDRR_H 0x0\
0000006 CPM_AXI_SLV_MULTQ_BASE_ADDRR_L 0x10000000 CPM_AXI_SLV_XDMA_BASE_ADDRR_H 0x00000006 CPM_AXI_SLV_XDMA_BASE_ADDRR_L 0x11000000 CPM_CCIX_GUI_EN 0 CPM_CCIX_IS_MM_ONLY 0 CPM_CCIX_PARTIAL_CACHELINE_SUPPORT 0 CPM_CCIX_PORT_AGGREGATION_ENABLE 0 CPM_CCIX_RP_EN 0 CPM_CCIX_RSVRD_MEMORY_AGENT_TYPE_0 HA0 CPM_CCIX_RSVRD_MEMORY_AGENT_TYPE_1 HA0 CPM_CCIX_RSVRD_MEMORY_AGENT_TYPE_2 HA0 CPM_CCIX_RSVRD_MEMORY_AGENT_TYPE_3 HA0 CPM_CCIX_RSVRD_MEMORY_AGENT_TYPE_4 HA0 CPM_CCIX_RSVRD_MEMORY_AGENT_TYPE_5 HA0 CPM_C\
CIX_RSVRD_MEMORY_AGENT_TYPE_6 HA0 CPM_CCIX_RSVRD_MEMORY_AGENT_TYPE_7 HA0 CPM_CCIX_RSVRD_MEMORY_ATTRIB_0 Normal_Non_Cacheable_Memory CPM_CCIX_RSVRD_MEMORY_ATTRIB_1 Normal_Non_Cacheable_Memory CPM_CCIX_RSVRD_MEMORY_ATTRIB_2 Normal_Non_Cacheable_Memory CPM_CCIX_RSVRD_MEMORY_ATTRIB_3 Normal_Non_Cacheable_Memory CPM_CCIX_RSVRD_MEMORY_ATTRIB_4 Normal_Non_Cacheable_Memory CPM_CCIX_RSVRD_MEMORY_ATTRIB_5 Normal_Non_Cacheable_Memory CPM_CCIX_RSVRD_MEMORY_ATTRIB_6 Normal_Non_Cacheable_Memory CPM_CCIX_RSVRD\
_MEMORY_ATTRIB_7 Normal_Non_Cacheable_Memory CPM_CCIX_RSVRD_MEMORY_BASEADDRESS_0 0x00000000 CPM_CCIX_RSVRD_MEMORY_BASEADDRESS_1 0x00000000 CPM_CCIX_RSVRD_MEMORY_BASEADDRESS_2 0x00000000 CPM_CCIX_RSVRD_MEMORY_BASEADDRESS_3 0x00000000 CPM_CCIX_RSVRD_MEMORY_BASEADDRESS_4 0x00000000 CPM_CCIX_RSVRD_MEMORY_BASEADDRESS_5 0x00000000 CPM_CCIX_RSVRD_MEMORY_BASEADDRESS_6 0x00000000 CPM_CCIX_RSVRD_MEMORY_BASEADDRESS_7 0x00000000 CPM_CCIX_RSVRD_MEMORY_REGION_0 0 CPM_CCIX_RSVRD_MEMORY_REGION_1 0 CPM_CCIX_RSVR\
D_MEMORY_REGION_2 0 CPM_CCIX_RSVRD_MEMORY_REGION_3 0 CPM_CCIX_RSVRD_MEMORY_REGION_4 0 CPM_CCIX_RSVRD_MEMORY_REGION_5 0 CPM_CCIX_RSVRD_MEMORY_REGION_6 0 CPM_CCIX_RSVRD_MEMORY_REGION_7 0 CPM_CCIX_RSVRD_MEMORY_SIZE_0 4GB CPM_CCIX_RSVRD_MEMORY_SIZE_1 4GB CPM_CCIX_RSVRD_MEMORY_SIZE_2 4GB CPM_CCIX_RSVRD_MEMORY_SIZE_3 4GB CPM_CCIX_RSVRD_MEMORY_SIZE_4 4GB CPM_CCIX_RSVRD_MEMORY_SIZE_5 4GB CPM_CCIX_RSVRD_MEMORY_SIZE_6 4GB CPM_CCIX_RSVRD_MEMORY_SIZE_7 4GB CPM_CCIX_RSVRD_MEMORY_TYPE_0 Other_or_Non_Specified\
_Memory_Type CPM_CCIX_RSVRD_MEMORY_TYPE_1 Other_or_Non_Specified_Memory_Type CPM_CCIX_RSVRD_MEMORY_TYPE_2 Other_or_Non_Specified_Memory_Type CPM_CCIX_RSVRD_MEMORY_TYPE_3 Other_or_Non_Specified_Memory_Type CPM_CCIX_RSVRD_MEMORY_TYPE_4 Other_or_Non_Specified_Memory_Type CPM_CCIX_RSVRD_MEMORY_TYPE_5 Other_or_Non_Specified_Memory_Type CPM_CCIX_RSVRD_MEMORY_TYPE_6 Other_or_Non_Specified_Memory_Type CPM_CCIX_RSVRD_MEMORY_TYPE_7 Other_or_Non_Specified_Memory_Type CPM_CCIX_SELECT_AGENT None CPM_CDO_EN 0\
 CPM_CLRERR_LANE_MARGIN 0 CPM_CORE_REF_CTRL_ACT_FREQMHZ 899.991028 CPM_CORE_REF_CTRL_DIVISOR0 2 CPM_CORE_REF_CTRL_FREQMHZ 900 CPM_CPLL_CTRL_FBDIV 108 CPM_CPLL_CTRL_SRCSEL REF_CLK CPM_DBG_REF_CTRL_ACT_FREQMHZ 299.997009 CPM_DBG_REF_CTRL_DIVISOR0 6 CPM_DBG_REF_CTRL_FREQMHZ 300 CPM_DESIGN_USE_MODE 0 CPM_DMA_CREDIT_INIT_DEMUX 1 CPM_DMA_IS_MM_ONLY 0 CPM_LSBUS_REF_CTRL_ACT_FREQMHZ 149.998505 CPM_LSBUS_REF_CTRL_DIVISOR0 12 CPM_LSBUS_REF_CTRL_FREQMHZ 150 CPM_NUM_CCIX_CREDIT_LINKS 0 CPM_NUM_HNF_AGENTS 0 \
CPM_NUM_HOME_OR_SLAVE_AGENTS 0 CPM_NUM_REQ_AGENTS 0 CPM_NUM_SLAVE_AGENTS 0 CPM_PCIE0_ACS_CAP_ON 1 CPM_PCIE0_AER_CAP_ENABLED 1 CPM_PCIE0_ARI_CAP_ENABLED 1 CPM_PCIE0_ASYNC_MODE SRNS CPM_PCIE0_ATS_PRI_CAP_ON 0 CPM_PCIE0_AXIBAR_NUM 1 CPM_PCIE0_AXISTEN_IF_CC_ALIGNMENT_MODE DWORD_Aligned CPM_PCIE0_AXISTEN_IF_COMPL_TIMEOUT_REG0 BEBC20 CPM_PCIE0_AXISTEN_IF_COMPL_TIMEOUT_REG1 2FAF080 CPM_PCIE0_AXISTEN_IF_CQ_ALIGNMENT_MODE DWORD_Aligned CPM_PCIE0_AXISTEN_IF_CQ_POISON_DISCARD 1 CPM_PCIE0_AXISTEN_IF_ENABLE_\
256_TAGS 0 CPM_PCIE0_AXISTEN_IF_ENABLE_CLIENT_TAG 0 CPM_PCIE0_AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE 0 CPM_PCIE0_AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK 0 CPM_PCIE0_AXISTEN_IF_ENABLE_MSG_ROUTE 0 CPM_PCIE0_AXISTEN_IF_ENABLE_RX_MSG_INTFC 0 CPM_PCIE0_AXISTEN_IF_ENABLE_RX_TAG_SCALING 0 CPM_PCIE0_AXISTEN_IF_ENABLE_TX_TAG_SCALING 0 CPM_PCIE0_AXISTEN_IF_EXTEND_CPL_TIMEOUT 16ms_to_1s CPM_PCIE0_AXISTEN_IF_EXT_512 0 CPM_PCIE0_AXISTEN_IF_EXT_512_CC_STRADDLE 0 CPM_PCIE0_AXISTEN_IF_EXT_512_CQ_STRADDLE 0 CPM_PCIE0\
_AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE 0 CPM_PCIE0_AXISTEN_IF_EXT_512_RC_STRADDLE 0 CPM_PCIE0_AXISTEN_IF_EXT_512_RQ_STRADDLE 0 CPM_PCIE0_AXISTEN_IF_RC_ALIGNMENT_MODE DWORD_Aligned CPM_PCIE0_AXISTEN_IF_RC_STRADDLE 0 CPM_PCIE0_AXISTEN_IF_RQ_ALIGNMENT_MODE DWORD_Aligned CPM_PCIE0_AXISTEN_IF_RX_PARITY_EN 1 CPM_PCIE0_AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT 0 CPM_PCIE0_AXISTEN_IF_TX_PARITY_EN 0 CPM_PCIE0_AXISTEN_IF_WIDTH 64 CPM_PCIE0_AXISTEN_MSIX_VECTORS_PER_FUNCTION 8 CPM_PCIE0_AXISTEN_USER_SPARE 0 CPM_PCIE0_\
BRIDGE_AXI_SLAVE_IF 0 CPM_PCIE0_CCIX_EN 0 CPM_PCIE0_CCIX_OPT_TLP_GEN_AND_RECEPT_EN_CONTROL_INTERNAL 0 CPM_PCIE0_CCIX_VENDOR_ID 0 CPM_PCIE0_CFG_CTL_IF 0 CPM_PCIE0_CFG_EXT_IF 0 CPM_PCIE0_CFG_FC_IF 0 CPM_PCIE0_CFG_MGMT_IF 0 CPM_PCIE0_CFG_SPEC_4_0 0 CPM_PCIE0_CFG_STS_IF 0 CPM_PCIE0_CFG_VEND_ID 10EE CPM_PCIE0_CONTROLLER_ENABLE 0 CPM_PCIE0_COPY_PF0_ENABLED 0 CPM_PCIE0_COPY_PF0_QDMA_ENABLED 1 CPM_PCIE0_COPY_PF0_SRIOV_QDMA_ENABLED 1 CPM_PCIE0_COPY_SRIOV_PF0_ENABLED 1 CPM_PCIE0_COPY_XDMA_PF0_ENABLED 0 CP\
M_PCIE0_CORE_CLK_FREQ 500 CPM_PCIE0_CORE_EDR_CLK_FREQ 625 CPM_PCIE0_DMA_DATA_WIDTH 256bits CPM_PCIE0_DMA_ENABLE_SECURE 0 CPM_PCIE0_DMA_INTF AXI4 CPM_PCIE0_DMA_MASK 256bits CPM_PCIE0_DMA_METERING_ENABLE 1 CPM_PCIE0_DMA_MSI_RX_PIN_ENABLED FALSE CPM_PCIE0_DMA_ROOT_PORT 0 CPM_PCIE0_DSC_BYPASS_RD 0 CPM_PCIE0_DSC_BYPASS_WR 0 CPM_PCIE0_EDR_IF 0 CPM_PCIE0_EDR_LINK_SPEED None CPM_PCIE0_EN_PARITY 0 CPM_PCIE0_EXT_CFG_SPACE_MODE None CPM_PCIE0_EXT_PCIE_CFG_SPACE_ENABLED None CPM_PCIE0_FUNCTIONAL_MODE None C\
PM_PCIE0_LANE_REVERSAL_EN 1 CPM_PCIE0_LEGACY_EXT_PCIE_CFG_SPACE_ENABLED 0 CPM_PCIE0_LINK_DEBUG_AXIST_EN 0 CPM_PCIE0_LINK_DEBUG_EN 0 CPM_PCIE0_LINK_SPEED0_FOR_POWER GEN1 CPM_PCIE0_LINK_WIDTH0_FOR_POWER 0 CPM_PCIE0_MAILBOX_ENABLE 0 CPM_PCIE0_MAX_LINK_SPEED 2.5_GT/s CPM_PCIE0_MCAP_ENABLE 0 CPM_PCIE0_MESG_RSVD_IF 0 CPM_PCIE0_MESG_TRANSMIT_IF 0 CPM_PCIE0_MODE0_FOR_POWER NONE CPM_PCIE0_MODES None CPM_PCIE0_MODE_SELECTION Basic CPM_PCIE0_MSIX_RP_ENABLED 1 CPM_PCIE0_MSI_X_OPTIONS None CPM_PCIE0_NUM_USR_\
IRQ 1 CPM_PCIE0_PASID_IF 0 CPM_PCIE0_PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE 0 CPM_PCIE0_PF0_ARI_CAP_NEXT_FUNC 0 CPM_PCIE0_PF0_ARI_CAP_VER 1 CPM_PCIE0_PF0_ATS_CAP_ON 0 CPM_PCIE0_PF0_AXIBAR2PCIE_BASEADDR_0 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_BASEADDR_1 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_BASEADDR_2 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_BASEADDR_3 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_BASEADDR_4 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_BASEADDR_5 0x00000000000000\
00 CPM_PCIE0_PF0_AXIBAR2PCIE_BRIDGE_0 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_BRIDGE_1 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_BRIDGE_2 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_BRIDGE_3 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_BRIDGE_4 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_BRIDGE_5 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_HIGHADDR_0 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_HIGHADDR_1 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_HIGHADDR_2 0x0000000000000000 CPM_P\
CIE0_PF0_AXIBAR2PCIE_HIGHADDR_3 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_HIGHADDR_4 0x0000000000000000 CPM_PCIE0_PF0_AXIBAR2PCIE_HIGHADDR_5 0x0000000000000000 CPM_PCIE0_PF0_AXILITE_MASTER_64BIT 0 CPM_PCIE0_PF0_AXILITE_MASTER_ENABLED 0 CPM_PCIE0_PF0_AXILITE_MASTER_PREFETCHABLE 0 CPM_PCIE0_PF0_AXILITE_MASTER_SCALE Kilobytes CPM_PCIE0_PF0_AXILITE_MASTER_SIZE 128 CPM_PCIE0_PF0_AXIST_BYPASS_64BIT 0 CPM_PCIE0_PF0_AXIST_BYPASS_ENABLED 0 CPM_PCIE0_PF0_AXIST_BYPASS_PREFETCHABLE 0 CPM_PCIE0_PF0_AXIST_\
BYPASS_SCALE Kilobytes CPM_PCIE0_PF0_AXIST_BYPASS_SIZE 128 CPM_PCIE0_PF0_BAR0_64BIT 0 CPM_PCIE0_PF0_BAR0_BRIDGE_64BIT 0 CPM_PCIE0_PF0_BAR0_BRIDGE_ENABLED 0 CPM_PCIE0_PF0_BAR0_BRIDGE_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR0_BRIDGE_SCALE Kilobytes CPM_PCIE0_PF0_BAR0_BRIDGE_SIZE 4 CPM_PCIE0_PF0_BAR0_BRIDGE_TYPE Memory CPM_PCIE0_PF0_BAR0_ENABLED 1 CPM_PCIE0_PF0_BAR0_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR0_QDMA_64BIT 0 CPM_PCIE0_PF0_BAR0_QDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR0_QDMA_ENABLED 0 CPM_PCIE0_PF0_BAR0_QDMA_PRE\
FETCHABLE 0 CPM_PCIE0_PF0_BAR0_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR0_QDMA_SIZE 4 CPM_PCIE0_PF0_BAR0_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BAR0_SCALE Kilobytes CPM_PCIE0_PF0_BAR0_SIZE 128 CPM_PCIE0_PF0_BAR0_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF0_BAR0_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR0_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF0_BAR0_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR0_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR0_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF0_BAR0_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE\
0_PF0_BAR0_TYPE Memory CPM_PCIE0_PF0_BAR0_XDMA_64BIT 0 CPM_PCIE0_PF0_BAR0_XDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR0_XDMA_ENABLED 0 CPM_PCIE0_PF0_BAR0_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR0_XDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR0_XDMA_SIZE 4 CPM_PCIE0_PF0_BAR0_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BAR1_64BIT 0 CPM_PCIE0_PF0_BAR1_BRIDGE_ENABLED 0 CPM_PCIE0_PF0_BAR1_BRIDGE_SCALE Kilobytes CPM_PCIE0_PF0_BAR1_BRIDGE_SIZE 4 CPM_PCIE0_PF0_BAR1_BRIDGE_TYPE Memory CPM_PCIE0_PF0_BAR1_ENABLED 0 CPM_PCIE0_PF0_B\
AR1_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR1_QDMA_64BIT 0 CPM_PCIE0_PF0_BAR1_QDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR1_QDMA_ENABLED 0 CPM_PCIE0_PF0_BAR1_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR1_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR1_QDMA_SIZE 4 CPM_PCIE0_PF0_BAR1_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BAR1_SCALE Kilobytes CPM_PCIE0_PF0_BAR1_SIZE 4 CPM_PCIE0_PF0_BAR1_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF0_BAR1_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR1_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF0_BAR1_SRIOV_QDMA_PREFETCHABLE 0 \
CPM_PCIE0_PF0_BAR1_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR1_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF0_BAR1_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BAR1_TYPE Memory CPM_PCIE0_PF0_BAR1_XDMA_64BIT 0 CPM_PCIE0_PF0_BAR1_XDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR1_XDMA_ENABLED 0 CPM_PCIE0_PF0_BAR1_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR1_XDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR1_XDMA_SIZE 4 CPM_PCIE0_PF0_BAR1_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BAR2_64BIT 0 CPM_PCIE0_PF0_BAR2_BRIDGE_64BIT 0 CPM_PCIE0_PF0_B\
AR2_BRIDGE_ENABLED 0 CPM_PCIE0_PF0_BAR2_BRIDGE_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR2_BRIDGE_SCALE Kilobytes CPM_PCIE0_PF0_BAR2_BRIDGE_SIZE 4 CPM_PCIE0_PF0_BAR2_BRIDGE_TYPE Memory CPM_PCIE0_PF0_BAR2_ENABLED 0 CPM_PCIE0_PF0_BAR2_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR2_QDMA_64BIT 0 CPM_PCIE0_PF0_BAR2_QDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR2_QDMA_ENABLED 0 CPM_PCIE0_PF0_BAR2_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR2_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR2_QDMA_SIZE 4 CPM_PCIE0_PF0_BAR2_QDMA_TYPE AXI_Bridge_Master CPM_P\
CIE0_PF0_BAR2_SCALE Kilobytes CPM_PCIE0_PF0_BAR2_SIZE 4 CPM_PCIE0_PF0_BAR2_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF0_BAR2_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR2_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF0_BAR2_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR2_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR2_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF0_BAR2_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BAR2_TYPE Memory CPM_PCIE0_PF0_BAR2_XDMA_64BIT 0 CPM_PCIE0_PF0_BAR2_XDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR2_XDMA_ENABLED 0 CPM_PCIE0_PF0_\
BAR2_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR2_XDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR2_XDMA_SIZE 4 CPM_PCIE0_PF0_BAR2_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BAR3_64BIT 0 CPM_PCIE0_PF0_BAR3_BRIDGE_ENABLED 0 CPM_PCIE0_PF0_BAR3_BRIDGE_SCALE Kilobytes CPM_PCIE0_PF0_BAR3_BRIDGE_SIZE 4 CPM_PCIE0_PF0_BAR3_BRIDGE_TYPE Memory CPM_PCIE0_PF0_BAR3_ENABLED 0 CPM_PCIE0_PF0_BAR3_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR3_QDMA_64BIT 0 CPM_PCIE0_PF0_BAR3_QDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR3_QDMA_ENABLED 0 CPM_PCIE0_PF0_BAR3\
_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR3_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR3_QDMA_SIZE 4 CPM_PCIE0_PF0_BAR3_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BAR3_SCALE Kilobytes CPM_PCIE0_PF0_BAR3_SIZE 4 CPM_PCIE0_PF0_BAR3_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF0_BAR3_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR3_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF0_BAR3_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR3_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR3_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF0_BAR3_SRIOV_QDMA_TYPE AXI_Bridge_Master C\
PM_PCIE0_PF0_BAR3_TYPE Memory CPM_PCIE0_PF0_BAR3_XDMA_64BIT 0 CPM_PCIE0_PF0_BAR3_XDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR3_XDMA_ENABLED 0 CPM_PCIE0_PF0_BAR3_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR3_XDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR3_XDMA_SIZE 4 CPM_PCIE0_PF0_BAR3_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BAR4_64BIT 0 CPM_PCIE0_PF0_BAR4_BRIDGE_64BIT 0 CPM_PCIE0_PF0_BAR4_BRIDGE_ENABLED 0 CPM_PCIE0_PF0_BAR4_BRIDGE_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR4_BRIDGE_SCALE Kilobytes CPM_PCIE0_PF0_BAR4_BRIDGE_SIZE 4 \
CPM_PCIE0_PF0_BAR4_BRIDGE_TYPE Memory CPM_PCIE0_PF0_BAR4_ENABLED 0 CPM_PCIE0_PF0_BAR4_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR4_QDMA_64BIT 0 CPM_PCIE0_PF0_BAR4_QDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR4_QDMA_ENABLED 0 CPM_PCIE0_PF0_BAR4_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR4_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR4_QDMA_SIZE 4 CPM_PCIE0_PF0_BAR4_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BAR4_SCALE Kilobytes CPM_PCIE0_PF0_BAR4_SIZE 4 CPM_PCIE0_PF0_BAR4_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF0_BAR4_SRIOV_QDMA_AXCACHE 0 CPM\
_PCIE0_PF0_BAR4_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF0_BAR4_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR4_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR4_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF0_BAR4_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BAR4_TYPE Memory CPM_PCIE0_PF0_BAR4_XDMA_64BIT 0 CPM_PCIE0_PF0_BAR4_XDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR4_XDMA_ENABLED 0 CPM_PCIE0_PF0_BAR4_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR4_XDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR4_XDMA_SIZE 4 CPM_PCIE0_PF0_BAR4_XDMA_TYPE AXI_Bridge_M\
aster CPM_PCIE0_PF0_BAR5_64BIT 0 CPM_PCIE0_PF0_BAR5_BRIDGE_ENABLED 0 CPM_PCIE0_PF0_BAR5_BRIDGE_SCALE Kilobytes CPM_PCIE0_PF0_BAR5_BRIDGE_SIZE 4 CPM_PCIE0_PF0_BAR5_BRIDGE_TYPE Memory CPM_PCIE0_PF0_BAR5_ENABLED 0 CPM_PCIE0_PF0_BAR5_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR5_QDMA_64BIT 0 CPM_PCIE0_PF0_BAR5_QDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR5_QDMA_ENABLED 0 CPM_PCIE0_PF0_BAR5_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR5_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR5_QDMA_SIZE 4 CPM_PCIE0_PF0_BAR5_QDMA_TYPE AXI_Bridge_Maste\
r CPM_PCIE0_PF0_BAR5_SCALE Kilobytes CPM_PCIE0_PF0_BAR5_SIZE 4 CPM_PCIE0_PF0_BAR5_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF0_BAR5_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR5_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF0_BAR5_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR5_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR5_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF0_BAR5_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BAR5_TYPE Memory CPM_PCIE0_PF0_BAR5_XDMA_64BIT 0 CPM_PCIE0_PF0_BAR5_XDMA_AXCACHE 0 CPM_PCIE0_PF0_BAR5_XDMA_ENABLED 0 CPM_PCI\
E0_PF0_BAR5_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_BAR5_XDMA_SCALE Kilobytes CPM_PCIE0_PF0_BAR5_XDMA_SIZE 4 CPM_PCIE0_PF0_BAR5_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF0_BASE_CLASS_MENU Memory_controller CPM_PCIE0_PF0_BASE_CLASS_VALUE 05 CPM_PCIE0_PF0_CAPABILITY_POINTER 80 CPM_PCIE0_PF0_CFG_DEV_ID B03F CPM_PCIE0_PF0_CFG_REV_ID 0 CPM_PCIE0_PF0_CFG_SUBSYS_ID 7 CPM_PCIE0_PF0_CFG_SUBSYS_VEND_ID 10EE CPM_PCIE0_PF0_CLASS_CODE 58000 CPM_PCIE0_PF0_DEV_CAP_10B_TAG_EN 0 CPM_PCIE0_PF0_DEV_CAP_ENDPOINT_L0S_LATENC\
Y less_than_64ns CPM_PCIE0_PF0_DEV_CAP_ENDPOINT_L1S_LATENCY less_than_1us CPM_PCIE0_PF0_DEV_CAP_EXT_TAG_EN 0 CPM_PCIE0_PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE 0 CPM_PCIE0_PF0_DEV_CAP_MAX_PAYLOAD 1024_bytes CPM_PCIE0_PF0_DLL_FEATURE_CAP_ID 0 CPM_PCIE0_PF0_DLL_FEATURE_CAP_ON 0 CPM_PCIE0_PF0_DLL_FEATURE_CAP_VER 1 CPM_PCIE0_PF0_DSN_CAP_ENABLE 0 CPM_PCIE0_PF0_EXPANSION_ROM_ENABLED 0 CPM_PCIE0_PF0_EXPANSION_ROM_QDMA_ENABLED 0 CPM_PCIE0_PF0_EXPANSION_ROM_QDMA_SCALE Kilobytes CPM_PCIE0_PF0_EXPANSION_RO\
M_QDMA_SIZE 2 CPM_PCIE0_PF0_EXPANSION_ROM_SCALE Kilobytes CPM_PCIE0_PF0_EXPANSION_ROM_SIZE 2 CPM_PCIE0_PF0_INTERFACE_VALUE 00 CPM_PCIE0_PF0_INTERRUPT_PIN NONE CPM_PCIE0_PF0_LINK_CAP_ASPM_SUPPORT No_ASPM CPM_PCIE0_PF0_LINK_STATUS_SLOT_CLOCK_CONFIG 1 CPM_PCIE0_PF0_MARGINING_CAP_ID 0 CPM_PCIE0_PF0_MARGINING_CAP_ON 0 CPM_PCIE0_PF0_MARGINING_CAP_VER 1 CPM_PCIE0_PF0_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE0_PF0_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE0_PF0_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE0_PF0_MSIX_CAP_TABLE_OFFSET 40\
 CPM_PCIE0_PF0_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE0_PF0_MSIX_ENABLED 1 CPM_PCIE0_PF0_MSI_CAP_MULTIMSGCAP 1_vector CPM_PCIE0_PF0_MSI_CAP_PERVECMASKCAP 0 CPM_PCIE0_PF0_MSI_ENABLED 1 CPM_PCIE0_PF0_PASID_CAP_MAX_PASID_WIDTH 20 CPM_PCIE0_PF0_PASID_CAP_ON 0 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_AXIL_MASTER 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_AXIST_BYPASS 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_BRIDGE_0 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_BRIDGE_1 0x0000000000000000 CPM_PCIE0_PF0_PC\
IEBAR2AXIBAR_BRIDGE_2 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_BRIDGE_3 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_BRIDGE_4 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_BRIDGE_5 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_QDMA_0 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_QDMA_1 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_QDMA_2 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_QDMA_3 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_QDMA_4 0x0000000000000000 CPM_PCIE0_PF0\
_PCIEBAR2AXIBAR_QDMA_5 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_SRIOV_QDMA_0 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_SRIOV_QDMA_1 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_SRIOV_QDMA_2 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_SRIOV_QDMA_3 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_SRIOV_QDMA_4 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_SRIOV_QDMA_5 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_XDMA_0 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_XDMA_1 0\
x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_XDMA_2 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_XDMA_3 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_XDMA_4 0x0000000000000000 CPM_PCIE0_PF0_PCIEBAR2AXIBAR_XDMA_5 0x0000000000000000 CPM_PCIE0_PF0_PL16_CAP_ID 0 CPM_PCIE0_PF0_PL16_CAP_ON 0 CPM_PCIE0_PF0_PL16_CAP_VER 1 CPM_PCIE0_PF0_PM_CAP_ID 1 CPM_PCIE0_PF0_PM_CAP_PMESUPPORT_D0 1 CPM_PCIE0_PF0_PM_CAP_PMESUPPORT_D1 1 CPM_PCIE0_PF0_PM_CAP_PMESUPPORT_D3COLD 1 CPM_PCIE0_PF0_PM_CAP_PMESUPPORT_D3HO\
T 1 CPM_PCIE0_PF0_PM_CAP_SUPP_D1_STATE 1 CPM_PCIE0_PF0_PM_CAP_VER_ID 3 CPM_PCIE0_PF0_PM_CSR_NOSOFTRESET 1 CPM_PCIE0_PF0_PRI_CAP_ON 0 CPM_PCIE0_PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED 0 CPM_PCIE0_PF0_SRIOV_BAR0_64BIT 0 CPM_PCIE0_PF0_SRIOV_BAR0_ENABLED 1 CPM_PCIE0_PF0_SRIOV_BAR0_PREFETCHABLE 0 CPM_PCIE0_PF0_SRIOV_BAR0_SCALE Kilobytes CPM_PCIE0_PF0_SRIOV_BAR0_SIZE 2 CPM_PCIE0_PF0_SRIOV_BAR0_TYPE Memory CPM_PCIE0_PF0_SRIOV_BAR1_64BIT 0 CPM_PCIE0_PF0_SRIOV_BAR1_ENABLED 0 CPM_PCIE0_PF0_SRIOV_BAR1_PREFETCHA\
BLE 0 CPM_PCIE0_PF0_SRIOV_BAR1_SCALE Kilobytes CPM_PCIE0_PF0_SRIOV_BAR1_SIZE 4 CPM_PCIE0_PF0_SRIOV_BAR1_TYPE Memory CPM_PCIE0_PF0_SRIOV_BAR2_64BIT 0 CPM_PCIE0_PF0_SRIOV_BAR2_ENABLED 0 CPM_PCIE0_PF0_SRIOV_BAR2_PREFETCHABLE 0 CPM_PCIE0_PF0_SRIOV_BAR2_SCALE Kilobytes CPM_PCIE0_PF0_SRIOV_BAR2_SIZE 4 CPM_PCIE0_PF0_SRIOV_BAR2_TYPE Memory CPM_PCIE0_PF0_SRIOV_BAR3_64BIT 0 CPM_PCIE0_PF0_SRIOV_BAR3_ENABLED 0 CPM_PCIE0_PF0_SRIOV_BAR3_PREFETCHABLE 0 CPM_PCIE0_PF0_SRIOV_BAR3_SCALE Kilobytes CPM_PCIE0_PF0_SRI\
OV_BAR3_SIZE 4 CPM_PCIE0_PF0_SRIOV_BAR3_TYPE Memory CPM_PCIE0_PF0_SRIOV_BAR4_64BIT 0 CPM_PCIE0_PF0_SRIOV_BAR4_ENABLED 0 CPM_PCIE0_PF0_SRIOV_BAR4_PREFETCHABLE 0 CPM_PCIE0_PF0_SRIOV_BAR4_SCALE Kilobytes CPM_PCIE0_PF0_SRIOV_BAR4_SIZE 4 CPM_PCIE0_PF0_SRIOV_BAR4_TYPE Memory CPM_PCIE0_PF0_SRIOV_BAR5_64BIT 0 CPM_PCIE0_PF0_SRIOV_BAR5_ENABLED 0 CPM_PCIE0_PF0_SRIOV_BAR5_PREFETCHABLE 0 CPM_PCIE0_PF0_SRIOV_BAR5_SCALE Kilobytes CPM_PCIE0_PF0_SRIOV_BAR5_SIZE 4 CPM_PCIE0_PF0_SRIOV_BAR5_TYPE Memory CPM_PCIE0_PF\
0_SRIOV_CAP_ENABLE 0 CPM_PCIE0_PF0_SRIOV_CAP_INITIAL_VF 4 CPM_PCIE0_PF0_SRIOV_CAP_TOTAL_VF 0 CPM_PCIE0_PF0_SRIOV_CAP_VER 1 CPM_PCIE0_PF0_SRIOV_FIRST_VF_OFFSET 4 CPM_PCIE0_PF0_SRIOV_FUNC_DEP_LINK 0 CPM_PCIE0_PF0_SRIOV_SUPPORTED_PAGE_SIZE 553 CPM_PCIE0_PF0_SRIOV_VF_DEVICE_ID C03F CPM_PCIE0_PF0_SUB_CLASS_INTF_MENU Other_memory_controller CPM_PCIE0_PF0_SUB_CLASS_VALUE 80 CPM_PCIE0_PF0_TPHR_CAP_DEV_SPECIFIC_MODE 1 CPM_PCIE0_PF0_TPHR_CAP_ENABLE 0 CPM_PCIE0_PF0_TPHR_CAP_INT_VEC_MODE 1 CPM_PCIE0_PF0_TPH\
R_CAP_ST_TABLE_LOC ST_Table_not_present CPM_PCIE0_PF0_TPHR_CAP_ST_TABLE_SIZE 16 CPM_PCIE0_PF0_TPHR_CAP_VER 1 CPM_PCIE0_PF0_TPHR_ENABLE 0 CPM_PCIE0_PF0_USE_CLASS_CODE_LOOKUP_ASSISTANT 0 CPM_PCIE0_PF0_VC_ARB_CAPABILITY 0 CPM_PCIE0_PF0_VC_ARB_TBL_OFFSET 0 CPM_PCIE0_PF0_VC_CAP_ENABLED 0 CPM_PCIE0_PF0_VC_CAP_VER 1 CPM_PCIE0_PF0_VC_EXTENDED_COUNT 0 CPM_PCIE0_PF0_VC_LOW_PRIORITY_EXTENDED_COUNT 0 CPM_PCIE0_PF0_XDMA_64BIT 0 CPM_PCIE0_PF0_XDMA_ENABLED 0 CPM_PCIE0_PF0_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF0_XDMA\
_SCALE Kilobytes CPM_PCIE0_PF0_XDMA_SIZE 128 CPM_PCIE0_PF1_ARI_CAP_NEXT_FUNC 0 CPM_PCIE0_PF1_ATS_CAP_ON 0 CPM_PCIE0_PF1_AXILITE_MASTER_64BIT 0 CPM_PCIE0_PF1_AXILITE_MASTER_ENABLED 0 CPM_PCIE0_PF1_AXILITE_MASTER_PREFETCHABLE 0 CPM_PCIE0_PF1_AXILITE_MASTER_SCALE Kilobytes CPM_PCIE0_PF1_AXILITE_MASTER_SIZE 128 CPM_PCIE0_PF1_AXIST_BYPASS_64BIT 0 CPM_PCIE0_PF1_AXIST_BYPASS_ENABLED 0 CPM_PCIE0_PF1_AXIST_BYPASS_PREFETCHABLE 0 CPM_PCIE0_PF1_AXIST_BYPASS_SCALE Kilobytes CPM_PCIE0_PF1_AXIST_BYPASS_SIZE 12\
8 CPM_PCIE0_PF1_BAR0_64BIT 0 CPM_PCIE0_PF1_BAR0_ENABLED 1 CPM_PCIE0_PF1_BAR0_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR0_QDMA_64BIT 0 CPM_PCIE0_PF1_BAR0_QDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR0_QDMA_ENABLED 0 CPM_PCIE0_PF1_BAR0_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR0_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR0_QDMA_SIZE 4 CPM_PCIE0_PF1_BAR0_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR0_SCALE Kilobytes CPM_PCIE0_PF1_BAR0_SIZE 128 CPM_PCIE0_PF1_BAR0_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF1_BAR0_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_\
PF1_BAR0_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF1_BAR0_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR0_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR0_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF1_BAR0_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR0_TYPE Memory CPM_PCIE0_PF1_BAR0_XDMA_64BIT 0 CPM_PCIE0_PF1_BAR0_XDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR0_XDMA_ENABLED 0 CPM_PCIE0_PF1_BAR0_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR0_XDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR0_XDMA_SIZE 4 CPM_PCIE0_PF1_BAR0_XDMA_TYPE AXI_Bridge_Master C\
PM_PCIE0_PF1_BAR1_64BIT 0 CPM_PCIE0_PF1_BAR1_ENABLED 0 CPM_PCIE0_PF1_BAR1_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR1_QDMA_64BIT 0 CPM_PCIE0_PF1_BAR1_QDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR1_QDMA_ENABLED 0 CPM_PCIE0_PF1_BAR1_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR1_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR1_QDMA_SIZE 4 CPM_PCIE0_PF1_BAR1_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR1_SCALE Kilobytes CPM_PCIE0_PF1_BAR1_SIZE 4 CPM_PCIE0_PF1_BAR1_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF1_BAR1_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF1_B\
AR1_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF1_BAR1_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR1_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR1_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF1_BAR1_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR1_TYPE Memory CPM_PCIE0_PF1_BAR1_XDMA_64BIT 0 CPM_PCIE0_PF1_BAR1_XDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR1_XDMA_ENABLED 0 CPM_PCIE0_PF1_BAR1_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR1_XDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR1_XDMA_SIZE 4 CPM_PCIE0_PF1_BAR1_XDMA_TYPE AXI_Bridge_Master CPM_PC\
IE0_PF1_BAR2_64BIT 0 CPM_PCIE0_PF1_BAR2_ENABLED 0 CPM_PCIE0_PF1_BAR2_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR2_QDMA_64BIT 0 CPM_PCIE0_PF1_BAR2_QDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR2_QDMA_ENABLED 0 CPM_PCIE0_PF1_BAR2_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR2_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR2_QDMA_SIZE 4 CPM_PCIE0_PF1_BAR2_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR2_SCALE Kilobytes CPM_PCIE0_PF1_BAR2_SIZE 4 CPM_PCIE0_PF1_BAR2_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF1_BAR2_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR2_S\
RIOV_QDMA_ENABLED 0 CPM_PCIE0_PF1_BAR2_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR2_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR2_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF1_BAR2_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR2_TYPE Memory CPM_PCIE0_PF1_BAR2_XDMA_64BIT 0 CPM_PCIE0_PF1_BAR2_XDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR2_XDMA_ENABLED 0 CPM_PCIE0_PF1_BAR2_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR2_XDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR2_XDMA_SIZE 4 CPM_PCIE0_PF1_BAR2_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_P\
F1_BAR3_64BIT 0 CPM_PCIE0_PF1_BAR3_ENABLED 0 CPM_PCIE0_PF1_BAR3_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR3_QDMA_64BIT 0 CPM_PCIE0_PF1_BAR3_QDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR3_QDMA_ENABLED 0 CPM_PCIE0_PF1_BAR3_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR3_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR3_QDMA_SIZE 4 CPM_PCIE0_PF1_BAR3_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR3_SCALE Kilobytes CPM_PCIE0_PF1_BAR3_SIZE 4 CPM_PCIE0_PF1_BAR3_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF1_BAR3_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR3_SRIOV_\
QDMA_ENABLED 0 CPM_PCIE0_PF1_BAR3_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR3_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR3_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF1_BAR3_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR3_TYPE Memory CPM_PCIE0_PF1_BAR3_XDMA_64BIT 0 CPM_PCIE0_PF1_BAR3_XDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR3_XDMA_ENABLED 0 CPM_PCIE0_PF1_BAR3_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR3_XDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR3_XDMA_SIZE 4 CPM_PCIE0_PF1_BAR3_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BA\
R4_64BIT 0 CPM_PCIE0_PF1_BAR4_ENABLED 0 CPM_PCIE0_PF1_BAR4_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR4_QDMA_64BIT 0 CPM_PCIE0_PF1_BAR4_QDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR4_QDMA_ENABLED 0 CPM_PCIE0_PF1_BAR4_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR4_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR4_QDMA_SIZE 4 CPM_PCIE0_PF1_BAR4_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR4_SCALE Kilobytes CPM_PCIE0_PF1_BAR4_SIZE 4 CPM_PCIE0_PF1_BAR4_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF1_BAR4_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR4_SRIOV_QDMA_\
ENABLED 0 CPM_PCIE0_PF1_BAR4_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR4_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR4_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF1_BAR4_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR4_TYPE Memory CPM_PCIE0_PF1_BAR4_XDMA_64BIT 0 CPM_PCIE0_PF1_BAR4_XDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR4_XDMA_ENABLED 0 CPM_PCIE0_PF1_BAR4_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR4_XDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR4_XDMA_SIZE 4 CPM_PCIE0_PF1_BAR4_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR5_64\
BIT 0 CPM_PCIE0_PF1_BAR5_ENABLED 0 CPM_PCIE0_PF1_BAR5_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR5_QDMA_64BIT 0 CPM_PCIE0_PF1_BAR5_QDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR5_QDMA_ENABLED 0 CPM_PCIE0_PF1_BAR5_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR5_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR5_QDMA_SIZE 4 CPM_PCIE0_PF1_BAR5_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR5_SCALE Kilobytes CPM_PCIE0_PF1_BAR5_SIZE 4 CPM_PCIE0_PF1_BAR5_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF1_BAR5_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR5_SRIOV_QDMA_ENABL\
ED 0 CPM_PCIE0_PF1_BAR5_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR5_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR5_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF1_BAR5_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BAR5_TYPE Memory CPM_PCIE0_PF1_BAR5_XDMA_64BIT 0 CPM_PCIE0_PF1_BAR5_XDMA_AXCACHE 0 CPM_PCIE0_PF1_BAR5_XDMA_ENABLED 0 CPM_PCIE0_PF1_BAR5_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF1_BAR5_XDMA_SCALE Kilobytes CPM_PCIE0_PF1_BAR5_XDMA_SIZE 4 CPM_PCIE0_PF1_BAR5_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF1_BASE_CLASS_M\
ENU Memory_controller CPM_PCIE0_PF1_BASE_CLASS_VALUE 05 CPM_PCIE0_PF1_CAPABILITY_POINTER 80 CPM_PCIE0_PF1_CFG_DEV_ID B13F CPM_PCIE0_PF1_CFG_REV_ID 0 CPM_PCIE0_PF1_CFG_SUBSYS_ID 7 CPM_PCIE0_PF1_CFG_SUBSYS_VEND_ID 10EE CPM_PCIE0_PF1_CLASS_CODE 0x058000 CPM_PCIE0_PF1_DSN_CAP_ENABLE 0 CPM_PCIE0_PF1_EXPANSION_ROM_ENABLED 0 CPM_PCIE0_PF1_EXPANSION_ROM_QDMA_ENABLED 0 CPM_PCIE0_PF1_EXPANSION_ROM_QDMA_SCALE Kilobytes CPM_PCIE0_PF1_EXPANSION_ROM_QDMA_SIZE 2 CPM_PCIE0_PF1_EXPANSION_ROM_SCALE Kilobytes CPM_\
PCIE0_PF1_EXPANSION_ROM_SIZE 2 CPM_PCIE0_PF1_INTERFACE_VALUE 00 CPM_PCIE0_PF1_INTERRUPT_PIN NONE CPM_PCIE0_PF1_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE0_PF1_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE0_PF1_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE0_PF1_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE0_PF1_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE0_PF1_MSIX_ENABLED 1 CPM_PCIE0_PF1_MSI_CAP_MULTIMSGCAP 1_vector CPM_PCIE0_PF1_MSI_CAP_PERVECMASKCAP 0 CPM_PCIE0_PF1_MSI_ENABLED 1 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_AXIL_MASTER 0x0000000000000000 CPM_PCIE0_PF1_P\
CIEBAR2AXIBAR_AXIST_BYPASS 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_QDMA_0 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_QDMA_1 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_QDMA_2 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_QDMA_3 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_QDMA_4 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_QDMA_5 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_SRIOV_QDMA_0 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_SRIOV_QDMA_1 0x0000000000000000 CP\
M_PCIE0_PF1_PCIEBAR2AXIBAR_SRIOV_QDMA_2 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_SRIOV_QDMA_3 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_SRIOV_QDMA_4 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_SRIOV_QDMA_5 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_XDMA_0 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_XDMA_1 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_XDMA_2 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_XDMA_3 0x0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_XDMA_4 0x\
0000000000000000 CPM_PCIE0_PF1_PCIEBAR2AXIBAR_XDMA_5 0x0000000000000000 CPM_PCIE0_PF1_PRI_CAP_ON 0 CPM_PCIE0_PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED 0 CPM_PCIE0_PF1_SRIOV_BAR0_64BIT 0 CPM_PCIE0_PF1_SRIOV_BAR0_ENABLED 1 CPM_PCIE0_PF1_SRIOV_BAR0_PREFETCHABLE 0 CPM_PCIE0_PF1_SRIOV_BAR0_SCALE Kilobytes CPM_PCIE0_PF1_SRIOV_BAR0_SIZE 2 CPM_PCIE0_PF1_SRIOV_BAR0_TYPE Memory CPM_PCIE0_PF1_SRIOV_BAR1_64BIT 0 CPM_PCIE0_PF1_SRIOV_BAR1_ENABLED 0 CPM_PCIE0_PF1_SRIOV_BAR1_PREFETCHABLE 0 CPM_PCIE0_PF1_SRIOV_BAR1_SCA\
LE Kilobytes CPM_PCIE0_PF1_SRIOV_BAR1_SIZE 4 CPM_PCIE0_PF1_SRIOV_BAR1_TYPE Memory CPM_PCIE0_PF1_SRIOV_BAR2_64BIT 0 CPM_PCIE0_PF1_SRIOV_BAR2_ENABLED 0 CPM_PCIE0_PF1_SRIOV_BAR2_PREFETCHABLE 0 CPM_PCIE0_PF1_SRIOV_BAR2_SCALE Kilobytes CPM_PCIE0_PF1_SRIOV_BAR2_SIZE 4 CPM_PCIE0_PF1_SRIOV_BAR2_TYPE Memory CPM_PCIE0_PF1_SRIOV_BAR3_64BIT 0 CPM_PCIE0_PF1_SRIOV_BAR3_ENABLED 0 CPM_PCIE0_PF1_SRIOV_BAR3_PREFETCHABLE 0 CPM_PCIE0_PF1_SRIOV_BAR3_SCALE Kilobytes CPM_PCIE0_PF1_SRIOV_BAR3_SIZE 4 CPM_PCIE0_PF1_SRIOV\
_BAR3_TYPE Memory CPM_PCIE0_PF1_SRIOV_BAR4_64BIT 0 CPM_PCIE0_PF1_SRIOV_BAR4_ENABLED 0 CPM_PCIE0_PF1_SRIOV_BAR4_PREFETCHABLE 0 CPM_PCIE0_PF1_SRIOV_BAR4_SCALE Kilobytes CPM_PCIE0_PF1_SRIOV_BAR4_SIZE 4 CPM_PCIE0_PF1_SRIOV_BAR4_TYPE Memory CPM_PCIE0_PF1_SRIOV_BAR5_64BIT 0 CPM_PCIE0_PF1_SRIOV_BAR5_ENABLED 0 CPM_PCIE0_PF1_SRIOV_BAR5_PREFETCHABLE 0 CPM_PCIE0_PF1_SRIOV_BAR5_SCALE Kilobytes CPM_PCIE0_PF1_SRIOV_BAR5_SIZE 4 CPM_PCIE0_PF1_SRIOV_BAR5_TYPE Memory CPM_PCIE0_PF1_SRIOV_CAP_ENABLE 0 CPM_PCIE0_PF1\
_SRIOV_CAP_INITIAL_VF 4 CPM_PCIE0_PF1_SRIOV_CAP_TOTAL_VF 0 CPM_PCIE0_PF1_SRIOV_CAP_VER 1 CPM_PCIE0_PF1_SRIOV_FIRST_VF_OFFSET 7 CPM_PCIE0_PF1_SRIOV_FUNC_DEP_LINK 0 CPM_PCIE0_PF1_SRIOV_SUPPORTED_PAGE_SIZE 553 CPM_PCIE0_PF1_SRIOV_VF_DEVICE_ID C13F CPM_PCIE0_PF1_SUB_CLASS_INTF_MENU Other_memory_controller CPM_PCIE0_PF1_SUB_CLASS_VALUE 80 CPM_PCIE0_PF1_USE_CLASS_CODE_LOOKUP_ASSISTANT 1 CPM_PCIE0_PF1_VEND_ID 10EE CPM_PCIE0_PF1_XDMA_64BIT 0 CPM_PCIE0_PF1_XDMA_ENABLED 0 CPM_PCIE0_PF1_XDMA_PREFETCHABLE 0\
 CPM_PCIE0_PF1_XDMA_SCALE Kilobytes CPM_PCIE0_PF1_XDMA_SIZE 128 CPM_PCIE0_PF2_ARI_CAP_NEXT_FUNC 0 CPM_PCIE0_PF2_ATS_CAP_ON 0 CPM_PCIE0_PF2_AXILITE_MASTER_64BIT 0 CPM_PCIE0_PF2_AXILITE_MASTER_ENABLED 0 CPM_PCIE0_PF2_AXILITE_MASTER_PREFETCHABLE 0 CPM_PCIE0_PF2_AXILITE_MASTER_SCALE Kilobytes CPM_PCIE0_PF2_AXILITE_MASTER_SIZE 128 CPM_PCIE0_PF2_AXIST_BYPASS_64BIT 0 CPM_PCIE0_PF2_AXIST_BYPASS_ENABLED 0 CPM_PCIE0_PF2_AXIST_BYPASS_PREFETCHABLE 0 CPM_PCIE0_PF2_AXIST_BYPASS_SCALE Kilobytes CPM_PCIE0_PF2_A\
XIST_BYPASS_SIZE 128 CPM_PCIE0_PF2_BAR0_64BIT 0 CPM_PCIE0_PF2_BAR0_ENABLED 1 CPM_PCIE0_PF2_BAR0_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR0_QDMA_64BIT 0 CPM_PCIE0_PF2_BAR0_QDMA_AXCACHE 0 CPM_PCIE0_PF2_BAR0_QDMA_ENABLED 0 CPM_PCIE0_PF2_BAR0_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR0_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR0_QDMA_SIZE 4 CPM_PCIE0_PF2_BAR0_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF2_BAR0_SCALE Kilobytes CPM_PCIE0_PF2_BAR0_SIZE 128 CPM_PCIE0_PF2_BAR0_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF2_BAR0_SRIOV_QDMA_A\
XCACHE 0 CPM_PCIE0_PF2_BAR0_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF2_BAR0_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR0_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR0_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF2_BAR0_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF2_BAR0_TYPE Memory CPM_PCIE0_PF2_BAR0_XDMA_64BIT 0 CPM_PCIE0_PF2_BAR0_XDMA_AXCACHE 0 CPM_PCIE0_PF2_BAR0_XDMA_ENABLED 0 CPM_PCIE0_PF2_BAR0_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR0_XDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR0_XDMA_SIZE 4 CPM_PCIE0_PF2_BAR0_XDMA_TYPE \
AXI_Bridge_Master CPM_PCIE0_PF2_BAR1_64BIT 0 CPM_PCIE0_PF2_BAR1_ENABLED 0 CPM_PCIE0_PF2_BAR1_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR1_QDMA_64BIT 0 CPM_PCIE0_PF2_BAR1_QDMA_AXCACHE 0 CPM_PCIE0_PF2_BAR1_QDMA_ENABLED 0 CPM_PCIE0_PF2_BAR1_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR1_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR1_QDMA_SIZE 4 CPM_PCIE0_PF2_BAR1_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF2_BAR1_SCALE Kilobytes CPM_PCIE0_PF2_BAR1_SIZE 4 CPM_PCIE0_PF2_BAR1_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF2_BAR1_SRIOV_QDMA_AXCACH\
E 0 CPM_PCIE0_PF2_BAR1_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF2_BAR1_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR1_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR1_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF2_BAR1_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF2_BAR1_TYPE Memory CPM_PCIE0_PF2_BAR1_XDMA_64BIT 0 CPM_PCIE0_PF2_BAR1_XDMA_AXCACHE 0 CPM_PCIE0_PF2_BAR1_XDMA_ENABLED 0 CPM_PCIE0_PF2_BAR1_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR1_XDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR1_XDMA_SIZE 4 CPM_PCIE0_PF2_BAR1_XDMA_TYPE AXI_B\
ridge_Master CPM_PCIE0_PF2_BAR2_64BIT 0 CPM_PCIE0_PF2_BAR2_ENABLED 0 CPM_PCIE0_PF2_BAR2_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR2_QDMA_64BIT 0 CPM_PCIE0_PF2_BAR2_QDMA_AXCACHE 0 CPM_PCIE0_PF2_BAR2_QDMA_ENABLED 0 CPM_PCIE0_PF2_BAR2_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR2_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR2_QDMA_SIZE 4 CPM_PCIE0_PF2_BAR2_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF2_BAR2_SCALE Kilobytes CPM_PCIE0_PF2_BAR2_SIZE 4 CPM_PCIE0_PF2_BAR2_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF2_BAR2_SRIOV_QDMA_AXCACHE 0 C\
PM_PCIE0_PF2_BAR2_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF2_BAR2_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR2_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR2_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF2_BAR2_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF2_BAR2_TYPE Memory CPM_PCIE0_PF2_BAR2_XDMA_64BIT 0 CPM_PCIE0_PF2_BAR2_XDMA_AXCACHE 0 CPM_PCIE0_PF2_BAR2_XDMA_ENABLED 0 CPM_PCIE0_PF2_BAR2_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR2_XDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR2_XDMA_SIZE 4 CPM_PCIE0_PF2_BAR2_XDMA_TYPE AXI_Bridge\
_Master CPM_PCIE0_PF2_BAR3_64BIT 0 CPM_PCIE0_PF2_BAR3_ENABLED 0 CPM_PCIE0_PF2_BAR3_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR3_QDMA_64BIT 0 CPM_PCIE0_PF2_BAR3_QDMA_AXCACHE 0 CPM_PCIE0_PF2_BAR3_QDMA_ENABLED 0 CPM_PCIE0_PF2_BAR3_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR3_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR3_QDMA_SIZE 4 CPM_PCIE0_PF2_BAR3_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF2_BAR3_SCALE Kilobytes CPM_PCIE0_PF2_BAR3_SIZE 4 CPM_PCIE0_PF2_BAR3_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF2_BAR3_SRIOV_QDMA_AXCACHE 0 CPM_PC\
IE0_PF2_BAR3_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF2_BAR3_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR3_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR3_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF2_BAR3_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF2_BAR3_TYPE Memory CPM_PCIE0_PF2_BAR3_XDMA_64BIT 0 CPM_PCIE0_PF2_BAR3_XDMA_AXCACHE 0 CPM_PCIE0_PF2_BAR3_XDMA_ENABLED 0 CPM_PCIE0_PF2_BAR3_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR3_XDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR3_XDMA_SIZE 4 CPM_PCIE0_PF2_BAR3_XDMA_TYPE AXI_Bridge_Mast\
er CPM_PCIE0_PF2_BAR4_64BIT 0 CPM_PCIE0_PF2_BAR4_ENABLED 0 CPM_PCIE0_PF2_BAR4_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR4_QDMA_64BIT 0 CPM_PCIE0_PF2_BAR4_QDMA_AXCACHE 0 CPM_PCIE0_PF2_BAR4_QDMA_ENABLED 0 CPM_PCIE0_PF2_BAR4_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR4_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR4_QDMA_SIZE 4 CPM_PCIE0_PF2_BAR4_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF2_BAR4_SCALE Kilobytes CPM_PCIE0_PF2_BAR4_SIZE 4 CPM_PCIE0_PF2_BAR4_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF2_BAR4_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_P\
F2_BAR4_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF2_BAR4_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR4_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR4_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF2_BAR4_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF2_BAR4_TYPE Memory CPM_PCIE0_PF2_BAR4_XDMA_64BIT 0 CPM_PCIE0_PF2_BAR4_XDMA_AXCACHE 0 CPM_PCIE0_PF2_BAR4_XDMA_ENABLED 0 CPM_PCIE0_PF2_BAR4_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR4_XDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR4_XDMA_SIZE 4 CPM_PCIE0_PF2_BAR4_XDMA_TYPE AXI_Bridge_Master CP\
M_PCIE0_PF2_BAR5_64BIT 0 CPM_PCIE0_PF2_BAR5_ENABLED 0 CPM_PCIE0_PF2_BAR5_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR5_QDMA_64BIT 0 CPM_PCIE0_PF2_BAR5_QDMA_AXCACHE 0 CPM_PCIE0_PF2_BAR5_QDMA_ENABLED 0 CPM_PCIE0_PF2_BAR5_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR5_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR5_QDMA_SIZE 4 CPM_PCIE0_PF2_BAR5_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF2_BAR5_SCALE Kilobytes CPM_PCIE0_PF2_BAR5_SIZE 4 CPM_PCIE0_PF2_BAR5_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF2_BAR5_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF2_BA\
R5_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF2_BAR5_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR5_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR5_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF2_BAR5_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF2_BAR5_TYPE Memory CPM_PCIE0_PF2_BAR5_XDMA_64BIT 0 CPM_PCIE0_PF2_BAR5_XDMA_AXCACHE 0 CPM_PCIE0_PF2_BAR5_XDMA_ENABLED 0 CPM_PCIE0_PF2_BAR5_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_BAR5_XDMA_SCALE Kilobytes CPM_PCIE0_PF2_BAR5_XDMA_SIZE 4 CPM_PCIE0_PF2_BAR5_XDMA_TYPE AXI_Bridge_Master CPM_PCI\
E0_PF2_BASE_CLASS_MENU Memory_controller CPM_PCIE0_PF2_BASE_CLASS_VALUE 05 CPM_PCIE0_PF2_CAPABILITY_POINTER 80 CPM_PCIE0_PF2_CFG_DEV_ID B23F CPM_PCIE0_PF2_CFG_REV_ID 0 CPM_PCIE0_PF2_CFG_SUBSYS_ID 7 CPM_PCIE0_PF2_CFG_SUBSYS_VEND_ID 10EE CPM_PCIE0_PF2_CLASS_CODE 0x058000 CPM_PCIE0_PF2_DSN_CAP_ENABLE 0 CPM_PCIE0_PF2_EXPANSION_ROM_ENABLED 0 CPM_PCIE0_PF2_EXPANSION_ROM_QDMA_ENABLED 0 CPM_PCIE0_PF2_EXPANSION_ROM_QDMA_SCALE Kilobytes CPM_PCIE0_PF2_EXPANSION_ROM_QDMA_SIZE 2 CPM_PCIE0_PF2_EXPANSION_ROM_S\
CALE Kilobytes CPM_PCIE0_PF2_EXPANSION_ROM_SIZE 2 CPM_PCIE0_PF2_INTERFACE_VALUE 00 CPM_PCIE0_PF2_INTERRUPT_PIN NONE CPM_PCIE0_PF2_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE0_PF2_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE0_PF2_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE0_PF2_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE0_PF2_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE0_PF2_MSIX_ENABLED 1 CPM_PCIE0_PF2_MSI_CAP_MULTIMSGCAP 1_vector CPM_PCIE0_PF2_MSI_CAP_PERVECMASKCAP 0 CPM_PCIE0_PF2_MSI_ENABLED 1 CPM_PCIE0_PF2_PASID_CAP_MAX_PASID_WIDTH 20 CPM_PCIE0_PF2\
_PCIEBAR2AXIBAR_AXIL_MASTER 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_AXIST_BYPASS 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_QDMA_0 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_QDMA_1 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_QDMA_2 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_QDMA_3 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_QDMA_4 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_QDMA_5 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_SRIOV_QDMA_0 0x0000000000000000 C\
PM_PCIE0_PF2_PCIEBAR2AXIBAR_SRIOV_QDMA_1 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_SRIOV_QDMA_2 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_SRIOV_QDMA_3 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_SRIOV_QDMA_4 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_SRIOV_QDMA_5 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_XDMA_0 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_XDMA_1 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_XDMA_2 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_XD\
MA_3 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_XDMA_4 0x0000000000000000 CPM_PCIE0_PF2_PCIEBAR2AXIBAR_XDMA_5 0x0000000000000000 CPM_PCIE0_PF2_PRI_CAP_ON 0 CPM_PCIE0_PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED 0 CPM_PCIE0_PF2_SRIOV_BAR0_64BIT 0 CPM_PCIE0_PF2_SRIOV_BAR0_ENABLED 1 CPM_PCIE0_PF2_SRIOV_BAR0_PREFETCHABLE 0 CPM_PCIE0_PF2_SRIOV_BAR0_SCALE Kilobytes CPM_PCIE0_PF2_SRIOV_BAR0_SIZE 2 CPM_PCIE0_PF2_SRIOV_BAR0_TYPE Memory CPM_PCIE0_PF2_SRIOV_BAR1_64BIT 0 CPM_PCIE0_PF2_SRIOV_BAR1_ENABLED 0 CPM_PC\
IE0_PF2_SRIOV_BAR1_PREFETCHABLE 0 CPM_PCIE0_PF2_SRIOV_BAR1_SCALE Kilobytes CPM_PCIE0_PF2_SRIOV_BAR1_SIZE 4 CPM_PCIE0_PF2_SRIOV_BAR1_TYPE Memory CPM_PCIE0_PF2_SRIOV_BAR2_64BIT 0 CPM_PCIE0_PF2_SRIOV_BAR2_ENABLED 0 CPM_PCIE0_PF2_SRIOV_BAR2_PREFETCHABLE 0 CPM_PCIE0_PF2_SRIOV_BAR2_SCALE Kilobytes CPM_PCIE0_PF2_SRIOV_BAR2_SIZE 4 CPM_PCIE0_PF2_SRIOV_BAR2_TYPE Memory CPM_PCIE0_PF2_SRIOV_BAR3_64BIT 0 CPM_PCIE0_PF2_SRIOV_BAR3_ENABLED 0 CPM_PCIE0_PF2_SRIOV_BAR3_PREFETCHABLE 0 CPM_PCIE0_PF2_SRIOV_BAR3_SCALE\
 Kilobytes CPM_PCIE0_PF2_SRIOV_BAR3_SIZE 4 CPM_PCIE0_PF2_SRIOV_BAR3_TYPE Memory CPM_PCIE0_PF2_SRIOV_BAR4_64BIT 0 CPM_PCIE0_PF2_SRIOV_BAR4_ENABLED 0 CPM_PCIE0_PF2_SRIOV_BAR4_PREFETCHABLE 0 CPM_PCIE0_PF2_SRIOV_BAR4_SCALE Kilobytes CPM_PCIE0_PF2_SRIOV_BAR4_SIZE 4 CPM_PCIE0_PF2_SRIOV_BAR4_TYPE Memory CPM_PCIE0_PF2_SRIOV_BAR5_64BIT 0 CPM_PCIE0_PF2_SRIOV_BAR5_ENABLED 0 CPM_PCIE0_PF2_SRIOV_BAR5_PREFETCHABLE 0 CPM_PCIE0_PF2_SRIOV_BAR5_SCALE Kilobytes CPM_PCIE0_PF2_SRIOV_BAR5_SIZE 4 CPM_PCIE0_PF2_SRIOV_B\
AR5_TYPE Memory CPM_PCIE0_PF2_SRIOV_CAP_ENABLE 0 CPM_PCIE0_PF2_SRIOV_CAP_INITIAL_VF 4 CPM_PCIE0_PF2_SRIOV_CAP_TOTAL_VF 0 CPM_PCIE0_PF2_SRIOV_CAP_VER 1 CPM_PCIE0_PF2_SRIOV_FIRST_VF_OFFSET 10 CPM_PCIE0_PF2_SRIOV_FUNC_DEP_LINK 0 CPM_PCIE0_PF2_SRIOV_SUPPORTED_PAGE_SIZE 553 CPM_PCIE0_PF2_SRIOV_VF_DEVICE_ID C23F CPM_PCIE0_PF2_SUB_CLASS_INTF_MENU Other_memory_controller CPM_PCIE0_PF2_SUB_CLASS_VALUE 80 CPM_PCIE0_PF2_USE_CLASS_CODE_LOOKUP_ASSISTANT 1 CPM_PCIE0_PF2_VEND_ID 10EE CPM_PCIE0_PF2_XDMA_64BIT 0\
 CPM_PCIE0_PF2_XDMA_ENABLED 0 CPM_PCIE0_PF2_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF2_XDMA_SCALE Kilobytes CPM_PCIE0_PF2_XDMA_SIZE 128 CPM_PCIE0_PF3_ARI_CAP_NEXT_FUNC 0 CPM_PCIE0_PF3_ATS_CAP_ON 0 CPM_PCIE0_PF3_AXILITE_MASTER_64BIT 0 CPM_PCIE0_PF3_AXILITE_MASTER_ENABLED 0 CPM_PCIE0_PF3_AXILITE_MASTER_PREFETCHABLE 0 CPM_PCIE0_PF3_AXILITE_MASTER_SCALE Kilobytes CPM_PCIE0_PF3_AXILITE_MASTER_SIZE 128 CPM_PCIE0_PF3_AXIST_BYPASS_64BIT 0 CPM_PCIE0_PF3_AXIST_BYPASS_ENABLED 0 CPM_PCIE0_PF3_AXIST_BYPASS_PREFETCHAB\
LE 0 CPM_PCIE0_PF3_AXIST_BYPASS_SCALE Kilobytes CPM_PCIE0_PF3_AXIST_BYPASS_SIZE 128 CPM_PCIE0_PF3_BAR0_64BIT 0 CPM_PCIE0_PF3_BAR0_ENABLED 1 CPM_PCIE0_PF3_BAR0_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR0_QDMA_64BIT 0 CPM_PCIE0_PF3_BAR0_QDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR0_QDMA_ENABLED 0 CPM_PCIE0_PF3_BAR0_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR0_QDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR0_QDMA_SIZE 4 CPM_PCIE0_PF3_BAR0_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR0_SCALE Kilobytes CPM_PCIE0_PF3_BAR0_SIZE 128 CPM_PC\
IE0_PF3_BAR0_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF3_BAR0_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR0_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF3_BAR0_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR0_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR0_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF3_BAR0_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR0_TYPE Memory CPM_PCIE0_PF3_BAR0_XDMA_64BIT 0 CPM_PCIE0_PF3_BAR0_XDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR0_XDMA_ENABLED 0 CPM_PCIE0_PF3_BAR0_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR0_XDMA_SCALE Kilobyt\
es CPM_PCIE0_PF3_BAR0_XDMA_SIZE 4 CPM_PCIE0_PF3_BAR0_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR1_64BIT 0 CPM_PCIE0_PF3_BAR1_ENABLED 0 CPM_PCIE0_PF3_BAR1_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR1_QDMA_64BIT 0 CPM_PCIE0_PF3_BAR1_QDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR1_QDMA_ENABLED 0 CPM_PCIE0_PF3_BAR1_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR1_QDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR1_QDMA_SIZE 4 CPM_PCIE0_PF3_BAR1_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR1_SCALE Kilobytes CPM_PCIE0_PF3_BAR1_SIZE 4 CPM_PCIE0_P\
F3_BAR1_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF3_BAR1_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR1_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF3_BAR1_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR1_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR1_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF3_BAR1_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR1_TYPE Memory CPM_PCIE0_PF3_BAR1_XDMA_64BIT 0 CPM_PCIE0_PF3_BAR1_XDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR1_XDMA_ENABLED 0 CPM_PCIE0_PF3_BAR1_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR1_XDMA_SCALE Kilobytes CP\
M_PCIE0_PF3_BAR1_XDMA_SIZE 4 CPM_PCIE0_PF3_BAR1_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR2_64BIT 0 CPM_PCIE0_PF3_BAR2_ENABLED 0 CPM_PCIE0_PF3_BAR2_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR2_QDMA_64BIT 0 CPM_PCIE0_PF3_BAR2_QDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR2_QDMA_ENABLED 0 CPM_PCIE0_PF3_BAR2_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR2_QDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR2_QDMA_SIZE 4 CPM_PCIE0_PF3_BAR2_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR2_SCALE Kilobytes CPM_PCIE0_PF3_BAR2_SIZE 4 CPM_PCIE0_PF3_BA\
R2_SRIOV_QDMA_64BIT 0 CPM_PCIE0_PF3_BAR2_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR2_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF3_BAR2_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR2_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR2_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF3_BAR2_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR2_TYPE Memory CPM_PCIE0_PF3_BAR2_XDMA_64BIT 0 CPM_PCIE0_PF3_BAR2_XDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR2_XDMA_ENABLED 0 CPM_PCIE0_PF3_BAR2_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR2_XDMA_SCALE Kilobytes CPM_PCI\
E0_PF3_BAR2_XDMA_SIZE 4 CPM_PCIE0_PF3_BAR2_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR3_64BIT 0 CPM_PCIE0_PF3_BAR3_ENABLED 0 CPM_PCIE0_PF3_BAR3_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR3_QDMA_64BIT 0 CPM_PCIE0_PF3_BAR3_QDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR3_QDMA_ENABLED 0 CPM_PCIE0_PF3_BAR3_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR3_QDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR3_QDMA_SIZE 4 CPM_PCIE0_PF3_BAR3_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR3_SCALE Kilobytes CPM_PCIE0_PF3_BAR3_SIZE 4 CPM_PCIE0_PF3_BAR3_SR\
IOV_QDMA_64BIT 0 CPM_PCIE0_PF3_BAR3_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR3_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF3_BAR3_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR3_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR3_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF3_BAR3_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR3_TYPE Memory CPM_PCIE0_PF3_BAR3_XDMA_64BIT 0 CPM_PCIE0_PF3_BAR3_XDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR3_XDMA_ENABLED 0 CPM_PCIE0_PF3_BAR3_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR3_XDMA_SCALE Kilobytes CPM_PCIE0_PF\
3_BAR3_XDMA_SIZE 4 CPM_PCIE0_PF3_BAR3_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR4_64BIT 0 CPM_PCIE0_PF3_BAR4_ENABLED 0 CPM_PCIE0_PF3_BAR4_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR4_QDMA_64BIT 0 CPM_PCIE0_PF3_BAR4_QDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR4_QDMA_ENABLED 0 CPM_PCIE0_PF3_BAR4_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR4_QDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR4_QDMA_SIZE 4 CPM_PCIE0_PF3_BAR4_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR4_SCALE Kilobytes CPM_PCIE0_PF3_BAR4_SIZE 4 CPM_PCIE0_PF3_BAR4_SRIOV_Q\
DMA_64BIT 0 CPM_PCIE0_PF3_BAR4_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR4_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF3_BAR4_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR4_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR4_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF3_BAR4_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR4_TYPE Memory CPM_PCIE0_PF3_BAR4_XDMA_64BIT 0 CPM_PCIE0_PF3_BAR4_XDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR4_XDMA_ENABLED 0 CPM_PCIE0_PF3_BAR4_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR4_XDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR\
4_XDMA_SIZE 4 CPM_PCIE0_PF3_BAR4_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR5_64BIT 0 CPM_PCIE0_PF3_BAR5_ENABLED 0 CPM_PCIE0_PF3_BAR5_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR5_QDMA_64BIT 0 CPM_PCIE0_PF3_BAR5_QDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR5_QDMA_ENABLED 0 CPM_PCIE0_PF3_BAR5_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR5_QDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR5_QDMA_SIZE 4 CPM_PCIE0_PF3_BAR5_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR5_SCALE Kilobytes CPM_PCIE0_PF3_BAR5_SIZE 4 CPM_PCIE0_PF3_BAR5_SRIOV_QDMA_6\
4BIT 0 CPM_PCIE0_PF3_BAR5_SRIOV_QDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR5_SRIOV_QDMA_ENABLED 0 CPM_PCIE0_PF3_BAR5_SRIOV_QDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR5_SRIOV_QDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR5_SRIOV_QDMA_SIZE 4 CPM_PCIE0_PF3_BAR5_SRIOV_QDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BAR5_TYPE Memory CPM_PCIE0_PF3_BAR5_XDMA_64BIT 0 CPM_PCIE0_PF3_BAR5_XDMA_AXCACHE 0 CPM_PCIE0_PF3_BAR5_XDMA_ENABLED 0 CPM_PCIE0_PF3_BAR5_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_BAR5_XDMA_SCALE Kilobytes CPM_PCIE0_PF3_BAR5_XDM\
A_SIZE 4 CPM_PCIE0_PF3_BAR5_XDMA_TYPE AXI_Bridge_Master CPM_PCIE0_PF3_BASE_CLASS_MENU Memory_controller CPM_PCIE0_PF3_BASE_CLASS_VALUE 05 CPM_PCIE0_PF3_CAPABILITY_POINTER 80 CPM_PCIE0_PF3_CFG_DEV_ID B33F CPM_PCIE0_PF3_CFG_REV_ID 0 CPM_PCIE0_PF3_CFG_SUBSYS_ID 7 CPM_PCIE0_PF3_CFG_SUBSYS_VEND_ID 10EE CPM_PCIE0_PF3_CLASS_CODE 0x058000 CPM_PCIE0_PF3_DSN_CAP_ENABLE 0 CPM_PCIE0_PF3_EXPANSION_ROM_ENABLED 0 CPM_PCIE0_PF3_EXPANSION_ROM_QDMA_ENABLED 0 CPM_PCIE0_PF3_EXPANSION_ROM_QDMA_SCALE Kilobytes CPM_PC\
IE0_PF3_EXPANSION_ROM_QDMA_SIZE 2 CPM_PCIE0_PF3_EXPANSION_ROM_SCALE Kilobytes CPM_PCIE0_PF3_EXPANSION_ROM_SIZE 2 CPM_PCIE0_PF3_INTERFACE_VALUE 00 CPM_PCIE0_PF3_INTERRUPT_PIN NONE CPM_PCIE0_PF3_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE0_PF3_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE0_PF3_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE0_PF3_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE0_PF3_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE0_PF3_MSIX_ENABLED 1 CPM_PCIE0_PF3_MSI_CAP_MULTIMSGCAP 1_vector CPM_PCIE0_PF3_MSI_CAP_PERVECMASKCAP 0 CPM_PCIE0_PF3_MSI_ENA\
BLED 1 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_AXIL_MASTER 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_AXIST_BYPASS 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_QDMA_0 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_QDMA_1 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_QDMA_2 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_QDMA_3 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_QDMA_4 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_QDMA_5 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_SRIOV_QDMA_0 \
0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_SRIOV_QDMA_1 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_SRIOV_QDMA_2 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_SRIOV_QDMA_3 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_SRIOV_QDMA_4 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_SRIOV_QDMA_5 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_XDMA_0 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_XDMA_1 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_XDMA_2 0x0000000000000000 CPM_PCIE0_P\
F3_PCIEBAR2AXIBAR_XDMA_3 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_XDMA_4 0x0000000000000000 CPM_PCIE0_PF3_PCIEBAR2AXIBAR_XDMA_5 0x0000000000000000 CPM_PCIE0_PF3_PRI_CAP_ON 0 CPM_PCIE0_PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED 0 CPM_PCIE0_PF3_SRIOV_BAR0_64BIT 0 CPM_PCIE0_PF3_SRIOV_BAR0_ENABLED 1 CPM_PCIE0_PF3_SRIOV_BAR0_PREFETCHABLE 0 CPM_PCIE0_PF3_SRIOV_BAR0_SCALE Kilobytes CPM_PCIE0_PF3_SRIOV_BAR0_SIZE 2 CPM_PCIE0_PF3_SRIOV_BAR0_TYPE Memory CPM_PCIE0_PF3_SRIOV_BAR1_64BIT 0 CPM_PCIE0_PF3_SRIOV_B\
AR1_ENABLED 0 CPM_PCIE0_PF3_SRIOV_BAR1_PREFETCHABLE 0 CPM_PCIE0_PF3_SRIOV_BAR1_SCALE Kilobytes CPM_PCIE0_PF3_SRIOV_BAR1_SIZE 4 CPM_PCIE0_PF3_SRIOV_BAR1_TYPE Memory CPM_PCIE0_PF3_SRIOV_BAR2_64BIT 0 CPM_PCIE0_PF3_SRIOV_BAR2_ENABLED 0 CPM_PCIE0_PF3_SRIOV_BAR2_PREFETCHABLE 0 CPM_PCIE0_PF3_SRIOV_BAR2_SCALE Kilobytes CPM_PCIE0_PF3_SRIOV_BAR2_SIZE 4 CPM_PCIE0_PF3_SRIOV_BAR2_TYPE Memory CPM_PCIE0_PF3_SRIOV_BAR3_64BIT 0 CPM_PCIE0_PF3_SRIOV_BAR3_ENABLED 0 CPM_PCIE0_PF3_SRIOV_BAR3_PREFETCHABLE 0 CPM_PCIE0_\
PF3_SRIOV_BAR3_SCALE Kilobytes CPM_PCIE0_PF3_SRIOV_BAR3_SIZE 4 CPM_PCIE0_PF3_SRIOV_BAR3_TYPE Memory CPM_PCIE0_PF3_SRIOV_BAR4_64BIT 0 CPM_PCIE0_PF3_SRIOV_BAR4_ENABLED 0 CPM_PCIE0_PF3_SRIOV_BAR4_PREFETCHABLE 0 CPM_PCIE0_PF3_SRIOV_BAR4_SCALE Kilobytes CPM_PCIE0_PF3_SRIOV_BAR4_SIZE 4 CPM_PCIE0_PF3_SRIOV_BAR4_TYPE Memory CPM_PCIE0_PF3_SRIOV_BAR5_64BIT 0 CPM_PCIE0_PF3_SRIOV_BAR5_ENABLED 0 CPM_PCIE0_PF3_SRIOV_BAR5_PREFETCHABLE 0 CPM_PCIE0_PF3_SRIOV_BAR5_SCALE Kilobytes CPM_PCIE0_PF3_SRIOV_BAR5_SIZE 4 C\
PM_PCIE0_PF3_SRIOV_BAR5_TYPE Memory CPM_PCIE0_PF3_SRIOV_CAP_ENABLE 0 CPM_PCIE0_PF3_SRIOV_CAP_INITIAL_VF 4 CPM_PCIE0_PF3_SRIOV_CAP_TOTAL_VF 0 CPM_PCIE0_PF3_SRIOV_CAP_VER 1 CPM_PCIE0_PF3_SRIOV_FIRST_VF_OFFSET 13 CPM_PCIE0_PF3_SRIOV_FUNC_DEP_LINK 0 CPM_PCIE0_PF3_SRIOV_SUPPORTED_PAGE_SIZE 553 CPM_PCIE0_PF3_SRIOV_VF_DEVICE_ID C33F CPM_PCIE0_PF3_SUB_CLASS_INTF_MENU Other_memory_controller CPM_PCIE0_PF3_SUB_CLASS_VALUE 80 CPM_PCIE0_PF3_USE_CLASS_CODE_LOOKUP_ASSISTANT 1 CPM_PCIE0_PF3_VEND_ID 10EE CPM_PC\
IE0_PF3_XDMA_64BIT 0 CPM_PCIE0_PF3_XDMA_ENABLED 0 CPM_PCIE0_PF3_XDMA_PREFETCHABLE 0 CPM_PCIE0_PF3_XDMA_SCALE Kilobytes CPM_PCIE0_PF3_XDMA_SIZE 128 CPM_PCIE0_PFx_MSI_ENABLED 4 CPM_PCIE0_PL_LINK_CAP_MAX_LINK_SPEED Gen3 CPM_PCIE0_PL_LINK_CAP_MAX_LINK_WIDTH NONE CPM_PCIE0_PL_UPSTREAM_FACING 1 CPM_PCIE0_PL_USER_SPARE 0 CPM_PCIE0_PM_ASPML0S_TIMEOUT 0 CPM_PCIE0_PM_ASPML1_ENTRY_DELAY 0 CPM_PCIE0_PM_ENABLE_L23_ENTRY 0 CPM_PCIE0_PM_ENABLE_SLOT_POWER_CAPTURE 1 CPM_PCIE0_PM_L1_REENTRY_DELAY 0 CPM_PCIE0_PM_P\
ME_TURNOFF_ACK_DELAY 0 CPM_PCIE0_PORT_TYPE PCI_Express_Endpoint_device CPM_PCIE0_QDMA_MULTQ_MAX 2048 CPM_PCIE0_QDMA_PARITY_SETTINGS None CPM_PCIE0_REF_CLK_FREQ 100_MHz CPM_PCIE0_SRIOV_CAP_ENABLE 0 CPM_PCIE0_SRIOV_FIRST_VF_OFFSET 4 CPM_PCIE0_TANDEM None CPM_PCIE0_TL2CFG_IF_PARITY_CHK 0 CPM_PCIE0_TL_NP_FIFO_NUM_TLPS 0 CPM_PCIE0_TL_PF_ENABLE_REG 1 CPM_PCIE0_TL_POSTED_RAM_SIZE 0 CPM_PCIE0_TL_USER_SPARE 0 CPM_PCIE0_TX_FC_IF 0 CPM_PCIE0_TYPE1_MEMBASE_MEMLIMIT_BRIDGE_ENABLE Disabled CPM_PCIE0_TYPE1_MEM\
BASE_MEMLIMIT_ENABLE Disabled CPM_PCIE0_TYPE1_PREFETCHABLE_MEMBASE_BRIDGE_MEMLIMIT Disabled CPM_PCIE0_TYPE1_PREFETCHABLE_MEMBASE_MEMLIMIT Disabled CPM_PCIE0_USER_CLK2_FREQ 125_MHz CPM_PCIE0_USER_CLK_FREQ 125_MHz CPM_PCIE0_USER_EDR_CLK2_FREQ 312.5_MHz CPM_PCIE0_USER_EDR_CLK_FREQ 312.5_MHz CPM_PCIE0_VC0_CAPABILITY_POINTER 80 CPM_PCIE0_VC1_BASE_DISABLE 0 CPM_PCIE0_VFG0_ATS_CAP_ON 0 CPM_PCIE0_VFG0_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE0_VFG0_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE0_VFG0_MSIX_CAP_TABLE_BIR BAR_0 CP\
M_PCIE0_VFG0_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE0_VFG0_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE0_VFG0_MSIX_ENABLED 1 CPM_PCIE0_VFG0_PRI_CAP_ON 0 CPM_PCIE0_VFG1_ATS_CAP_ON 0 CPM_PCIE0_VFG1_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE0_VFG1_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE0_VFG1_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE0_VFG1_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE0_VFG1_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE0_VFG1_MSIX_ENABLED 1 CPM_PCIE0_VFG1_PRI_CAP_ON 0 CPM_PCIE0_VFG2_ATS_CAP_ON 0 CPM_PCIE0_VFG2_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE0_VFG2_MSI\
X_CAP_PBA_OFFSET 50 CPM_PCIE0_VFG2_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE0_VFG2_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE0_VFG2_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE0_VFG2_MSIX_ENABLED 1 CPM_PCIE0_VFG2_PRI_CAP_ON 0 CPM_PCIE0_VFG3_ATS_CAP_ON 0 CPM_PCIE0_VFG3_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE0_VFG3_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE0_VFG3_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE0_VFG3_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE0_VFG3_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE0_VFG3_MSIX_ENABLED 1 CPM_PCIE0_VFG3_PRI_CAP_ON 0 CPM_PCIE0_XDMA_AXILITE\
_SLAVE_IF 0 CPM_PCIE0_XDMA_AXI_ID_WIDTH 2 CPM_PCIE0_XDMA_DSC_BYPASS_RD 0000 CPM_PCIE0_XDMA_DSC_BYPASS_WR 0000 CPM_PCIE0_XDMA_EDGE_INTERRUPT 0 CPM_PCIE0_XDMA_IRQ 1 CPM_PCIE0_XDMA_PARITY_SETTINGS None CPM_PCIE0_XDMA_RNUM_CHNL 1 CPM_PCIE0_XDMA_RNUM_RIDS 2 CPM_PCIE0_XDMA_STS_PORTS 0 CPM_PCIE0_XDMA_WNUM_CHNL 1 CPM_PCIE0_XDMA_WNUM_RIDS 2 CPM_PCIE1_ACS_CAP_ON 1 CPM_PCIE1_AER_CAP_ENABLED 1 CPM_PCIE1_ARI_CAP_ENABLED 1 CPM_PCIE1_ASYNC_MODE SRNS CPM_PCIE1_ATS_PRI_CAP_ON 0 CPM_PCIE1_AXIBAR_NUM 1 CPM_PCIE1_A\
XISTEN_IF_CC_ALIGNMENT_MODE DWORD_Aligned CPM_PCIE1_AXISTEN_IF_COMPL_TIMEOUT_REG0 BEBC20 CPM_PCIE1_AXISTEN_IF_COMPL_TIMEOUT_REG1 2FAF080 CPM_PCIE1_AXISTEN_IF_CQ_ALIGNMENT_MODE DWORD_Aligned CPM_PCIE1_AXISTEN_IF_CQ_POISON_DISCARD 1 CPM_PCIE1_AXISTEN_IF_ENABLE_256_TAGS 0 CPM_PCIE1_AXISTEN_IF_ENABLE_CLIENT_TAG 0 CPM_PCIE1_AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE 0 CPM_PCIE1_AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK 0 CPM_PCIE1_AXISTEN_IF_ENABLE_MSG_ROUTE 0 CPM_PCIE1_AXISTEN_IF_ENABLE_RX_MSG_INTFC 0 CPM_PCIE\
1_AXISTEN_IF_ENABLE_RX_TAG_SCALING 0 CPM_PCIE1_AXISTEN_IF_ENABLE_TX_TAG_SCALING 0 CPM_PCIE1_AXISTEN_IF_EXTEND_CPL_TIMEOUT 16ms_to_1s CPM_PCIE1_AXISTEN_IF_EXT_512 0 CPM_PCIE1_AXISTEN_IF_EXT_512_CC_STRADDLE 0 CPM_PCIE1_AXISTEN_IF_EXT_512_CQ_STRADDLE 0 CPM_PCIE1_AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE 1 CPM_PCIE1_AXISTEN_IF_EXT_512_RC_STRADDLE 0 CPM_PCIE1_AXISTEN_IF_EXT_512_RQ_STRADDLE 0 CPM_PCIE1_AXISTEN_IF_RC_ALIGNMENT_MODE DWORD_Aligned CPM_PCIE1_AXISTEN_IF_RC_STRADDLE 1 CPM_PCIE1_AXISTEN_IF_RQ_ALIG\
NMENT_MODE DWORD_Aligned CPM_PCIE1_AXISTEN_IF_RX_PARITY_EN 1 CPM_PCIE1_AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT 0 CPM_PCIE1_AXISTEN_IF_TX_PARITY_EN 0 CPM_PCIE1_AXISTEN_IF_WIDTH 64 CPM_PCIE1_AXISTEN_MSIX_VECTORS_PER_FUNCTION 8 CPM_PCIE1_AXISTEN_USER_SPARE 0 CPM_PCIE1_CCIX_EN 0 CPM_PCIE1_CCIX_OPT_TLP_GEN_AND_RECEPT_EN_CONTROL_INTERNAL 0 CPM_PCIE1_CCIX_VENDOR_ID 0 CPM_PCIE1_CFG_CTL_IF 0 CPM_PCIE1_CFG_EXT_IF 0 CPM_PCIE1_CFG_FC_IF 0 CPM_PCIE1_CFG_MGMT_IF 0 CPM_PCIE1_CFG_SPEC_4_0 0 CPM_PCIE1_CFG_STS_IF 0 CPM_\
PCIE1_CFG_VEND_ID 10EE CPM_PCIE1_CONTROLLER_ENABLE 0 CPM_PCIE1_COPY_PF0_ENABLED 0 CPM_PCIE1_COPY_SRIOV_PF0_ENABLED 1 CPM_PCIE1_CORE_CLK_FREQ 500 CPM_PCIE1_CORE_EDR_CLK_FREQ 625 CPM_PCIE1_DSC_BYPASS_RD 0 CPM_PCIE1_DSC_BYPASS_WR 0 CPM_PCIE1_EDR_IF 0 CPM_PCIE1_EDR_LINK_SPEED None CPM_PCIE1_EN_PARITY 0 CPM_PCIE1_EXT_PCIE_CFG_SPACE_ENABLED None CPM_PCIE1_FUNCTIONAL_MODE None CPM_PCIE1_LANE_REVERSAL_EN 1 CPM_PCIE1_LEGACY_EXT_PCIE_CFG_SPACE_ENABLED 0 CPM_PCIE1_LINK_DEBUG_AXIST_EN 0 CPM_PCIE1_LINK_DEBUG\
_EN 0 CPM_PCIE1_LINK_SPEED1_FOR_POWER GEN1 CPM_PCIE1_LINK_WIDTH1_FOR_POWER 0 CPM_PCIE1_MAX_LINK_SPEED 2.5_GT/s CPM_PCIE1_MCAP_ENABLE 0 CPM_PCIE1_MESG_RSVD_IF 0 CPM_PCIE1_MESG_TRANSMIT_IF 0 CPM_PCIE1_MODE1_FOR_POWER NONE CPM_PCIE1_MODES None CPM_PCIE1_MODE_SELECTION Basic CPM_PCIE1_MSIX_RP_ENABLED 1 CPM_PCIE1_MSI_X_OPTIONS None CPM_PCIE1_PASID_IF 0 CPM_PCIE1_PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE 0 CPM_PCIE1_PF0_ARI_CAP_NEXT_FUNC 0 CPM_PCIE1_PF0_ARI_CAP_VER 1 CPM_PCIE1_PF0_ATS_CAP_ON 0 CPM_PCIE1_\
PF0_AXILITE_MASTER_64BIT 0 CPM_PCIE1_PF0_AXILITE_MASTER_ENABLED 0 CPM_PCIE1_PF0_AXILITE_MASTER_PREFETCHABLE 0 CPM_PCIE1_PF0_AXILITE_MASTER_SCALE Kilobytes CPM_PCIE1_PF0_AXILITE_MASTER_SIZE 128 CPM_PCIE1_PF0_AXIST_BYPASS_64BIT 0 CPM_PCIE1_PF0_AXIST_BYPASS_ENABLED 0 CPM_PCIE1_PF0_AXIST_BYPASS_PREFETCHABLE 0 CPM_PCIE1_PF0_AXIST_BYPASS_SCALE Kilobytes CPM_PCIE1_PF0_AXIST_BYPASS_SIZE 128 CPM_PCIE1_PF0_BAR0_64BIT 0 CPM_PCIE1_PF0_BAR0_ENABLED 1 CPM_PCIE1_PF0_BAR0_PREFETCHABLE 0 CPM_PCIE1_PF0_BAR0_SCALE\
 Kilobytes CPM_PCIE1_PF0_BAR0_SIZE 128 CPM_PCIE1_PF0_BAR0_TYPE Memory CPM_PCIE1_PF0_BAR1_64BIT 0 CPM_PCIE1_PF0_BAR1_ENABLED 0 CPM_PCIE1_PF0_BAR1_PREFETCHABLE 0 CPM_PCIE1_PF0_BAR1_SCALE Kilobytes CPM_PCIE1_PF0_BAR1_SIZE 4 CPM_PCIE1_PF0_BAR1_TYPE Memory CPM_PCIE1_PF0_BAR2_64BIT 0 CPM_PCIE1_PF0_BAR2_ENABLED 0 CPM_PCIE1_PF0_BAR2_PREFETCHABLE 0 CPM_PCIE1_PF0_BAR2_SCALE Kilobytes CPM_PCIE1_PF0_BAR2_SIZE 4 CPM_PCIE1_PF0_BAR2_TYPE Memory CPM_PCIE1_PF0_BAR3_64BIT 0 CPM_PCIE1_PF0_BAR3_ENABLED 0 CPM_PCIE1_\
PF0_BAR3_PREFETCHABLE 0 CPM_PCIE1_PF0_BAR3_SCALE Kilobytes CPM_PCIE1_PF0_BAR3_SIZE 4 CPM_PCIE1_PF0_BAR3_TYPE Memory CPM_PCIE1_PF0_BAR4_64BIT 0 CPM_PCIE1_PF0_BAR4_ENABLED 0 CPM_PCIE1_PF0_BAR4_PREFETCHABLE 0 CPM_PCIE1_PF0_BAR4_SCALE Kilobytes CPM_PCIE1_PF0_BAR4_SIZE 4 CPM_PCIE1_PF0_BAR4_TYPE Memory CPM_PCIE1_PF0_BAR5_64BIT 0 CPM_PCIE1_PF0_BAR5_ENABLED 0 CPM_PCIE1_PF0_BAR5_PREFETCHABLE 0 CPM_PCIE1_PF0_BAR5_SCALE Kilobytes CPM_PCIE1_PF0_BAR5_SIZE 4 CPM_PCIE1_PF0_BAR5_TYPE Memory CPM_PCIE1_PF0_BASE_C\
LASS_MENU Memory_controller CPM_PCIE1_PF0_BASE_CLASS_VALUE 05 CPM_PCIE1_PF0_CAPABILITY_POINTER 80 CPM_PCIE1_PF0_CFG_DEV_ID B03F CPM_PCIE1_PF0_CFG_REV_ID 0 CPM_PCIE1_PF0_CFG_SUBSYS_ID 7 CPM_PCIE1_PF0_CFG_SUBSYS_VEND_ID 10EE CPM_PCIE1_PF0_CLASS_CODE 58000 CPM_PCIE1_PF0_DEV_CAP_10B_TAG_EN 0 CPM_PCIE1_PF0_DEV_CAP_ENDPOINT_L0S_LATENCY less_than_64ns CPM_PCIE1_PF0_DEV_CAP_ENDPOINT_L1S_LATENCY less_than_1us CPM_PCIE1_PF0_DEV_CAP_EXT_TAG_EN 0 CPM_PCIE1_PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE 0 CPM_PCIE\
1_PF0_DEV_CAP_MAX_PAYLOAD 1024_bytes CPM_PCIE1_PF0_DLL_FEATURE_CAP_ID 0 CPM_PCIE1_PF0_DLL_FEATURE_CAP_ON 0 CPM_PCIE1_PF0_DLL_FEATURE_CAP_VER 1 CPM_PCIE1_PF0_DSN_CAP_ENABLE 0 CPM_PCIE1_PF0_EXPANSION_ROM_ENABLED 0 CPM_PCIE1_PF0_EXPANSION_ROM_SCALE Kilobytes CPM_PCIE1_PF0_EXPANSION_ROM_SIZE 2 CPM_PCIE1_PF0_INTERFACE_VALUE 00 CPM_PCIE1_PF0_INTERRUPT_PIN NONE CPM_PCIE1_PF0_LINK_CAP_ASPM_SUPPORT No_ASPM CPM_PCIE1_PF0_LINK_STATUS_SLOT_CLOCK_CONFIG 1 CPM_PCIE1_PF0_MARGINING_CAP_ID 0 CPM_PCIE1_PF0_MARGIN\
ING_CAP_ON 0 CPM_PCIE1_PF0_MARGINING_CAP_VER 1 CPM_PCIE1_PF0_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE1_PF0_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE1_PF0_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE1_PF0_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE1_PF0_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE1_PF0_MSIX_ENABLED 1 CPM_PCIE1_PF0_MSI_CAP_MULTIMSGCAP 1_vector CPM_PCIE1_PF0_MSI_CAP_PERVECMASKCAP 0 CPM_PCIE1_PF0_MSI_ENABLED 1 CPM_PCIE1_PF0_PASID_CAP_MAX_PASID_WIDTH 20 CPM_PCIE1_PF0_PASID_CAP_ON 0 CPM_PCIE1_PF0_PCIEBAR2AXIBAR_AXIL_MASTER 0x0000000000\
000000 CPM_PCIE1_PF0_PCIEBAR2AXIBAR_AXIST_BYPASS 0x0000000000000000 CPM_PCIE1_PF0_PL16_CAP_ID 0 CPM_PCIE1_PF0_PL16_CAP_ON 0 CPM_PCIE1_PF0_PL16_CAP_VER 1 CPM_PCIE1_PF0_PM_CAP_ID 1 CPM_PCIE1_PF0_PM_CAP_PMESUPPORT_D0 1 CPM_PCIE1_PF0_PM_CAP_PMESUPPORT_D1 1 CPM_PCIE1_PF0_PM_CAP_PMESUPPORT_D3COLD 1 CPM_PCIE1_PF0_PM_CAP_PMESUPPORT_D3HOT 1 CPM_PCIE1_PF0_PM_CAP_SUPP_D1_STATE 1 CPM_PCIE1_PF0_PM_CAP_VER_ID 3 CPM_PCIE1_PF0_PM_CSR_NOSOFTRESET 1 CPM_PCIE1_PF0_PRI_CAP_ON 0 CPM_PCIE1_PF0_SRIOV_ARI_CAPBL_HIER_PR\
ESERVED 0 CPM_PCIE1_PF0_SRIOV_BAR0_64BIT 0 CPM_PCIE1_PF0_SRIOV_BAR0_ENABLED 1 CPM_PCIE1_PF0_SRIOV_BAR0_PREFETCHABLE 0 CPM_PCIE1_PF0_SRIOV_BAR0_SCALE Kilobytes CPM_PCIE1_PF0_SRIOV_BAR0_SIZE 2 CPM_PCIE1_PF0_SRIOV_BAR0_TYPE Memory CPM_PCIE1_PF0_SRIOV_BAR1_64BIT 0 CPM_PCIE1_PF0_SRIOV_BAR1_ENABLED 0 CPM_PCIE1_PF0_SRIOV_BAR1_PREFETCHABLE 0 CPM_PCIE1_PF0_SRIOV_BAR1_SCALE Kilobytes CPM_PCIE1_PF0_SRIOV_BAR1_SIZE 4 CPM_PCIE1_PF0_SRIOV_BAR1_TYPE Memory CPM_PCIE1_PF0_SRIOV_BAR2_64BIT 0 CPM_PCIE1_PF0_SRIOV_B\
AR2_ENABLED 0 CPM_PCIE1_PF0_SRIOV_BAR2_PREFETCHABLE 0 CPM_PCIE1_PF0_SRIOV_BAR2_SCALE Kilobytes CPM_PCIE1_PF0_SRIOV_BAR2_SIZE 4 CPM_PCIE1_PF0_SRIOV_BAR2_TYPE Memory CPM_PCIE1_PF0_SRIOV_BAR3_64BIT 0 CPM_PCIE1_PF0_SRIOV_BAR3_ENABLED 0 CPM_PCIE1_PF0_SRIOV_BAR3_PREFETCHABLE 0 CPM_PCIE1_PF0_SRIOV_BAR3_SCALE Kilobytes CPM_PCIE1_PF0_SRIOV_BAR3_SIZE 4 CPM_PCIE1_PF0_SRIOV_BAR3_TYPE Memory CPM_PCIE1_PF0_SRIOV_BAR4_64BIT 0 CPM_PCIE1_PF0_SRIOV_BAR4_ENABLED 0 CPM_PCIE1_PF0_SRIOV_BAR4_PREFETCHABLE 0 CPM_PCIE1_\
PF0_SRIOV_BAR4_SCALE Kilobytes CPM_PCIE1_PF0_SRIOV_BAR4_SIZE 4 CPM_PCIE1_PF0_SRIOV_BAR4_TYPE Memory CPM_PCIE1_PF0_SRIOV_BAR5_64BIT 0 CPM_PCIE1_PF0_SRIOV_BAR5_ENABLED 0 CPM_PCIE1_PF0_SRIOV_BAR5_PREFETCHABLE 0 CPM_PCIE1_PF0_SRIOV_BAR5_SCALE Kilobytes CPM_PCIE1_PF0_SRIOV_BAR5_SIZE 4 CPM_PCIE1_PF0_SRIOV_BAR5_TYPE Memory CPM_PCIE1_PF0_SRIOV_CAP_ENABLE 0 CPM_PCIE1_PF0_SRIOV_CAP_INITIAL_VF 4 CPM_PCIE1_PF0_SRIOV_CAP_TOTAL_VF 0 CPM_PCIE1_PF0_SRIOV_CAP_VER 1 CPM_PCIE1_PF0_SRIOV_FIRST_VF_OFFSET 4 CPM_PCIE1\
_PF0_SRIOV_FUNC_DEP_LINK 0 CPM_PCIE1_PF0_SRIOV_SUPPORTED_PAGE_SIZE 553 CPM_PCIE1_PF0_SRIOV_VF_DEVICE_ID C03F CPM_PCIE1_PF0_SUB_CLASS_INTF_MENU Other_memory_controller CPM_PCIE1_PF0_SUB_CLASS_VALUE 80 CPM_PCIE1_PF0_TPHR_CAP_DEV_SPECIFIC_MODE 1 CPM_PCIE1_PF0_TPHR_CAP_ENABLE 0 CPM_PCIE1_PF0_TPHR_CAP_INT_VEC_MODE 1 CPM_PCIE1_PF0_TPHR_CAP_ST_TABLE_LOC ST_Table_not_present CPM_PCIE1_PF0_TPHR_CAP_ST_TABLE_SIZE 16 CPM_PCIE1_PF0_TPHR_CAP_VER 1 CPM_PCIE1_PF0_TPHR_ENABLE 0 CPM_PCIE1_PF0_USE_CLASS_CODE_LOOK\
UP_ASSISTANT 0 CPM_PCIE1_PF0_VC_ARB_CAPABILITY 0 CPM_PCIE1_PF0_VC_ARB_TBL_OFFSET 0 CPM_PCIE1_PF0_VC_CAP_ENABLED 0 CPM_PCIE1_PF0_VC_CAP_VER 1 CPM_PCIE1_PF0_VC_EXTENDED_COUNT 0 CPM_PCIE1_PF0_VC_LOW_PRIORITY_EXTENDED_COUNT 0 CPM_PCIE1_PF1_ARI_CAP_NEXT_FUNC 0 CPM_PCIE1_PF1_ATS_CAP_ON 0 CPM_PCIE1_PF1_AXILITE_MASTER_64BIT 0 CPM_PCIE1_PF1_AXILITE_MASTER_ENABLED 0 CPM_PCIE1_PF1_AXILITE_MASTER_PREFETCHABLE 0 CPM_PCIE1_PF1_AXILITE_MASTER_SCALE Kilobytes CPM_PCIE1_PF1_AXILITE_MASTER_SIZE 128 CPM_PCIE1_PF1_\
AXIST_BYPASS_64BIT 0 CPM_PCIE1_PF1_AXIST_BYPASS_ENABLED 0 CPM_PCIE1_PF1_AXIST_BYPASS_PREFETCHABLE 0 CPM_PCIE1_PF1_AXIST_BYPASS_SCALE Kilobytes CPM_PCIE1_PF1_AXIST_BYPASS_SIZE 128 CPM_PCIE1_PF1_BAR0_64BIT 0 CPM_PCIE1_PF1_BAR0_ENABLED 1 CPM_PCIE1_PF1_BAR0_PREFETCHABLE 0 CPM_PCIE1_PF1_BAR0_SCALE Kilobytes CPM_PCIE1_PF1_BAR0_SIZE 128 CPM_PCIE1_PF1_BAR0_TYPE Memory CPM_PCIE1_PF1_BAR1_64BIT 0 CPM_PCIE1_PF1_BAR1_ENABLED 0 CPM_PCIE1_PF1_BAR1_PREFETCHABLE 0 CPM_PCIE1_PF1_BAR1_SCALE Kilobytes CPM_PCIE1_PF\
1_BAR1_SIZE 4 CPM_PCIE1_PF1_BAR1_TYPE Memory CPM_PCIE1_PF1_BAR2_64BIT 0 CPM_PCIE1_PF1_BAR2_ENABLED 0 CPM_PCIE1_PF1_BAR2_PREFETCHABLE 0 CPM_PCIE1_PF1_BAR2_SCALE Kilobytes CPM_PCIE1_PF1_BAR2_SIZE 4 CPM_PCIE1_PF1_BAR2_TYPE Memory CPM_PCIE1_PF1_BAR3_64BIT 0 CPM_PCIE1_PF1_BAR3_ENABLED 0 CPM_PCIE1_PF1_BAR3_PREFETCHABLE 0 CPM_PCIE1_PF1_BAR3_SCALE Kilobytes CPM_PCIE1_PF1_BAR3_SIZE 4 CPM_PCIE1_PF1_BAR3_TYPE Memory CPM_PCIE1_PF1_BAR4_64BIT 0 CPM_PCIE1_PF1_BAR4_ENABLED 0 CPM_PCIE1_PF1_BAR4_PREFETCHABLE 0 C\
PM_PCIE1_PF1_BAR4_SCALE Kilobytes CPM_PCIE1_PF1_BAR4_SIZE 4 CPM_PCIE1_PF1_BAR4_TYPE Memory CPM_PCIE1_PF1_BAR5_64BIT 0 CPM_PCIE1_PF1_BAR5_ENABLED 0 CPM_PCIE1_PF1_BAR5_PREFETCHABLE 0 CPM_PCIE1_PF1_BAR5_SCALE Kilobytes CPM_PCIE1_PF1_BAR5_SIZE 4 CPM_PCIE1_PF1_BAR5_TYPE Memory CPM_PCIE1_PF1_BASE_CLASS_MENU Memory_controller CPM_PCIE1_PF1_BASE_CLASS_VALUE 05 CPM_PCIE1_PF1_CAPABILITY_POINTER 80 CPM_PCIE1_PF1_CFG_DEV_ID B13F CPM_PCIE1_PF1_CFG_REV_ID 0 CPM_PCIE1_PF1_CFG_SUBSYS_ID 7 CPM_PCIE1_PF1_CFG_SUBS\
YS_VEND_ID 10EE CPM_PCIE1_PF1_CLASS_CODE 0x058000 CPM_PCIE1_PF1_DSN_CAP_ENABLE 0 CPM_PCIE1_PF1_EXPANSION_ROM_ENABLED 0 CPM_PCIE1_PF1_EXPANSION_ROM_SCALE Kilobytes CPM_PCIE1_PF1_EXPANSION_ROM_SIZE 2 CPM_PCIE1_PF1_INTERFACE_VALUE 00 CPM_PCIE1_PF1_INTERRUPT_PIN NONE CPM_PCIE1_PF1_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE1_PF1_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE1_PF1_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE1_PF1_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE1_PF1_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE1_PF1_MSIX_ENABLED 1 CPM_PCIE1_PF1_MSI\
_CAP_MULTIMSGCAP 1_vector CPM_PCIE1_PF1_MSI_CAP_PERVECMASKCAP 0 CPM_PCIE1_PF1_MSI_ENABLED 1 CPM_PCIE1_PF1_PCIEBAR2AXIBAR_AXIL_MASTER 0x0000000000000000 CPM_PCIE1_PF1_PCIEBAR2AXIBAR_AXIST_BYPASS 0x0000000000000000 CPM_PCIE1_PF1_PRI_CAP_ON 0 CPM_PCIE1_PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED 0 CPM_PCIE1_PF1_SRIOV_BAR0_64BIT 0 CPM_PCIE1_PF1_SRIOV_BAR0_ENABLED 1 CPM_PCIE1_PF1_SRIOV_BAR0_PREFETCHABLE 0 CPM_PCIE1_PF1_SRIOV_BAR0_SCALE Kilobytes CPM_PCIE1_PF1_SRIOV_BAR0_SIZE 2 CPM_PCIE1_PF1_SRIOV_BAR0_TYPE Me\
mory CPM_PCIE1_PF1_SRIOV_BAR1_64BIT 0 CPM_PCIE1_PF1_SRIOV_BAR1_ENABLED 0 CPM_PCIE1_PF1_SRIOV_BAR1_PREFETCHABLE 0 CPM_PCIE1_PF1_SRIOV_BAR1_SCALE Kilobytes CPM_PCIE1_PF1_SRIOV_BAR1_SIZE 4 CPM_PCIE1_PF1_SRIOV_BAR1_TYPE Memory CPM_PCIE1_PF1_SRIOV_BAR2_64BIT 0 CPM_PCIE1_PF1_SRIOV_BAR2_ENABLED 0 CPM_PCIE1_PF1_SRIOV_BAR2_PREFETCHABLE 0 CPM_PCIE1_PF1_SRIOV_BAR2_SCALE Kilobytes CPM_PCIE1_PF1_SRIOV_BAR2_SIZE 4 CPM_PCIE1_PF1_SRIOV_BAR2_TYPE Memory CPM_PCIE1_PF1_SRIOV_BAR3_64BIT 0 CPM_PCIE1_PF1_SRIOV_BAR3_E\
NABLED 0 CPM_PCIE1_PF1_SRIOV_BAR3_PREFETCHABLE 0 CPM_PCIE1_PF1_SRIOV_BAR3_SCALE Kilobytes CPM_PCIE1_PF1_SRIOV_BAR3_SIZE 4 CPM_PCIE1_PF1_SRIOV_BAR3_TYPE Memory CPM_PCIE1_PF1_SRIOV_BAR4_64BIT 0 CPM_PCIE1_PF1_SRIOV_BAR4_ENABLED 0 CPM_PCIE1_PF1_SRIOV_BAR4_PREFETCHABLE 0 CPM_PCIE1_PF1_SRIOV_BAR4_SCALE Kilobytes CPM_PCIE1_PF1_SRIOV_BAR4_SIZE 4 CPM_PCIE1_PF1_SRIOV_BAR4_TYPE Memory CPM_PCIE1_PF1_SRIOV_BAR5_64BIT 0 CPM_PCIE1_PF1_SRIOV_BAR5_ENABLED 0 CPM_PCIE1_PF1_SRIOV_BAR5_PREFETCHABLE 0 CPM_PCIE1_PF1_S\
RIOV_BAR5_SCALE Kilobytes CPM_PCIE1_PF1_SRIOV_BAR5_SIZE 4 CPM_PCIE1_PF1_SRIOV_BAR5_TYPE Memory CPM_PCIE1_PF1_SRIOV_CAP_ENABLE 0 CPM_PCIE1_PF1_SRIOV_CAP_INITIAL_VF 4 CPM_PCIE1_PF1_SRIOV_CAP_TOTAL_VF 0 CPM_PCIE1_PF1_SRIOV_CAP_VER 1 CPM_PCIE1_PF1_SRIOV_FIRST_VF_OFFSET 7 CPM_PCIE1_PF1_SRIOV_FUNC_DEP_LINK 0 CPM_PCIE1_PF1_SRIOV_SUPPORTED_PAGE_SIZE 553 CPM_PCIE1_PF1_SRIOV_VF_DEVICE_ID C13F CPM_PCIE1_PF1_SUB_CLASS_INTF_MENU Other_memory_controller CPM_PCIE1_PF1_SUB_CLASS_VALUE 80 CPM_PCIE1_PF1_USE_CLASS\
_CODE_LOOKUP_ASSISTANT 1 CPM_PCIE1_PF1_VEND_ID 10EE CPM_PCIE1_PF2_ARI_CAP_NEXT_FUNC 0 CPM_PCIE1_PF2_ATS_CAP_ON 0 CPM_PCIE1_PF2_AXILITE_MASTER_64BIT 0 CPM_PCIE1_PF2_AXILITE_MASTER_ENABLED 0 CPM_PCIE1_PF2_AXILITE_MASTER_PREFETCHABLE 0 CPM_PCIE1_PF2_AXILITE_MASTER_SCALE Kilobytes CPM_PCIE1_PF2_AXILITE_MASTER_SIZE 128 CPM_PCIE1_PF2_AXIST_BYPASS_64BIT 0 CPM_PCIE1_PF2_AXIST_BYPASS_ENABLED 0 CPM_PCIE1_PF2_AXIST_BYPASS_PREFETCHABLE 0 CPM_PCIE1_PF2_AXIST_BYPASS_SCALE Kilobytes CPM_PCIE1_PF2_AXIST_BYPASS_\
SIZE 128 CPM_PCIE1_PF2_BAR0_64BIT 0 CPM_PCIE1_PF2_BAR0_ENABLED 1 CPM_PCIE1_PF2_BAR0_PREFETCHABLE 0 CPM_PCIE1_PF2_BAR0_SCALE Kilobytes CPM_PCIE1_PF2_BAR0_SIZE 128 CPM_PCIE1_PF2_BAR0_TYPE Memory CPM_PCIE1_PF2_BAR1_64BIT 0 CPM_PCIE1_PF2_BAR1_ENABLED 0 CPM_PCIE1_PF2_BAR1_PREFETCHABLE 0 CPM_PCIE1_PF2_BAR1_SCALE Kilobytes CPM_PCIE1_PF2_BAR1_SIZE 4 CPM_PCIE1_PF2_BAR1_TYPE Memory CPM_PCIE1_PF2_BAR2_64BIT 0 CPM_PCIE1_PF2_BAR2_ENABLED 0 CPM_PCIE1_PF2_BAR2_PREFETCHABLE 0 CPM_PCIE1_PF2_BAR2_SCALE Kilobytes \
CPM_PCIE1_PF2_BAR2_SIZE 4 CPM_PCIE1_PF2_BAR2_TYPE Memory CPM_PCIE1_PF2_BAR3_64BIT 0 CPM_PCIE1_PF2_BAR3_ENABLED 0 CPM_PCIE1_PF2_BAR3_PREFETCHABLE 0 CPM_PCIE1_PF2_BAR3_SCALE Kilobytes CPM_PCIE1_PF2_BAR3_SIZE 4 CPM_PCIE1_PF2_BAR3_TYPE Memory CPM_PCIE1_PF2_BAR4_64BIT 0 CPM_PCIE1_PF2_BAR4_ENABLED 0 CPM_PCIE1_PF2_BAR4_PREFETCHABLE 0 CPM_PCIE1_PF2_BAR4_SCALE Kilobytes CPM_PCIE1_PF2_BAR4_SIZE 4 CPM_PCIE1_PF2_BAR4_TYPE Memory CPM_PCIE1_PF2_BAR5_64BIT 0 CPM_PCIE1_PF2_BAR5_ENABLED 0 CPM_PCIE1_PF2_BAR5_PREF\
ETCHABLE 0 CPM_PCIE1_PF2_BAR5_SCALE Kilobytes CPM_PCIE1_PF2_BAR5_SIZE 4 CPM_PCIE1_PF2_BAR5_TYPE Memory CPM_PCIE1_PF2_BASE_CLASS_MENU Memory_controller CPM_PCIE1_PF2_BASE_CLASS_VALUE 05 CPM_PCIE1_PF2_CAPABILITY_POINTER 80 CPM_PCIE1_PF2_CFG_DEV_ID B23F CPM_PCIE1_PF2_CFG_REV_ID 0 CPM_PCIE1_PF2_CFG_SUBSYS_ID 7 CPM_PCIE1_PF2_CFG_SUBSYS_VEND_ID 10EE CPM_PCIE1_PF2_CLASS_CODE 0x058000 CPM_PCIE1_PF2_DSN_CAP_ENABLE 0 CPM_PCIE1_PF2_EXPANSION_ROM_ENABLED 0 CPM_PCIE1_PF2_EXPANSION_ROM_SCALE Kilobytes CPM_PCI\
E1_PF2_EXPANSION_ROM_SIZE 2 CPM_PCIE1_PF2_INTERFACE_VALUE 00 CPM_PCIE1_PF2_INTERRUPT_PIN NONE CPM_PCIE1_PF2_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE1_PF2_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE1_PF2_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE1_PF2_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE1_PF2_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE1_PF2_MSIX_ENABLED 1 CPM_PCIE1_PF2_MSI_CAP_MULTIMSGCAP 1_vector CPM_PCIE1_PF2_MSI_CAP_PERVECMASKCAP 0 CPM_PCIE1_PF2_MSI_ENABLED 1 CPM_PCIE1_PF2_PASID_CAP_MAX_PASID_WIDTH 20 CPM_PCIE1_PF2_PCIEBAR2AXIBAR_AXIL_M\
ASTER 0x0000000000000000 CPM_PCIE1_PF2_PCIEBAR2AXIBAR_AXIST_BYPASS 0x0000000000000000 CPM_PCIE1_PF2_PRI_CAP_ON 0 CPM_PCIE1_PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED 0 CPM_PCIE1_PF2_SRIOV_BAR0_64BIT 0 CPM_PCIE1_PF2_SRIOV_BAR0_ENABLED 1 CPM_PCIE1_PF2_SRIOV_BAR0_PREFETCHABLE 0 CPM_PCIE1_PF2_SRIOV_BAR0_SCALE Kilobytes CPM_PCIE1_PF2_SRIOV_BAR0_SIZE 2 CPM_PCIE1_PF2_SRIOV_BAR0_TYPE Memory CPM_PCIE1_PF2_SRIOV_BAR1_64BIT 0 CPM_PCIE1_PF2_SRIOV_BAR1_ENABLED 0 CPM_PCIE1_PF2_SRIOV_BAR1_PREFETCHABLE 0 CPM_PCIE1_PF2_\
SRIOV_BAR1_SCALE Kilobytes CPM_PCIE1_PF2_SRIOV_BAR1_SIZE 4 CPM_PCIE1_PF2_SRIOV_BAR1_TYPE Memory CPM_PCIE1_PF2_SRIOV_BAR2_64BIT 0 CPM_PCIE1_PF2_SRIOV_BAR2_ENABLED 0 CPM_PCIE1_PF2_SRIOV_BAR2_PREFETCHABLE 0 CPM_PCIE1_PF2_SRIOV_BAR2_SCALE Kilobytes CPM_PCIE1_PF2_SRIOV_BAR2_SIZE 4 CPM_PCIE1_PF2_SRIOV_BAR2_TYPE Memory CPM_PCIE1_PF2_SRIOV_BAR3_64BIT 0 CPM_PCIE1_PF2_SRIOV_BAR3_ENABLED 0 CPM_PCIE1_PF2_SRIOV_BAR3_PREFETCHABLE 0 CPM_PCIE1_PF2_SRIOV_BAR3_SCALE Kilobytes CPM_PCIE1_PF2_SRIOV_BAR3_SIZE 4 CPM_P\
CIE1_PF2_SRIOV_BAR3_TYPE Memory CPM_PCIE1_PF2_SRIOV_BAR4_64BIT 0 CPM_PCIE1_PF2_SRIOV_BAR4_ENABLED 0 CPM_PCIE1_PF2_SRIOV_BAR4_PREFETCHABLE 0 CPM_PCIE1_PF2_SRIOV_BAR4_SCALE Kilobytes CPM_PCIE1_PF2_SRIOV_BAR4_SIZE 4 CPM_PCIE1_PF2_SRIOV_BAR4_TYPE Memory CPM_PCIE1_PF2_SRIOV_BAR5_64BIT 0 CPM_PCIE1_PF2_SRIOV_BAR5_ENABLED 0 CPM_PCIE1_PF2_SRIOV_BAR5_PREFETCHABLE 0 CPM_PCIE1_PF2_SRIOV_BAR5_SCALE Kilobytes CPM_PCIE1_PF2_SRIOV_BAR5_SIZE 4 CPM_PCIE1_PF2_SRIOV_BAR5_TYPE Memory CPM_PCIE1_PF2_SRIOV_CAP_ENABLE 0\
 CPM_PCIE1_PF2_SRIOV_CAP_INITIAL_VF 4 CPM_PCIE1_PF2_SRIOV_CAP_TOTAL_VF 0 CPM_PCIE1_PF2_SRIOV_CAP_VER 1 CPM_PCIE1_PF2_SRIOV_FIRST_VF_OFFSET 10 CPM_PCIE1_PF2_SRIOV_FUNC_DEP_LINK 0 CPM_PCIE1_PF2_SRIOV_SUPPORTED_PAGE_SIZE 553 CPM_PCIE1_PF2_SRIOV_VF_DEVICE_ID C23F CPM_PCIE1_PF2_SUB_CLASS_INTF_MENU Other_memory_controller CPM_PCIE1_PF2_SUB_CLASS_VALUE 80 CPM_PCIE1_PF2_USE_CLASS_CODE_LOOKUP_ASSISTANT 1 CPM_PCIE1_PF2_VEND_ID 10EE CPM_PCIE1_PF3_ARI_CAP_NEXT_FUNC 0 CPM_PCIE1_PF3_ATS_CAP_ON 0 CPM_PCIE1_PF3\
_AXILITE_MASTER_64BIT 0 CPM_PCIE1_PF3_AXILITE_MASTER_ENABLED 0 CPM_PCIE1_PF3_AXILITE_MASTER_PREFETCHABLE 0 CPM_PCIE1_PF3_AXILITE_MASTER_SCALE Kilobytes CPM_PCIE1_PF3_AXILITE_MASTER_SIZE 128 CPM_PCIE1_PF3_AXIST_BYPASS_64BIT 0 CPM_PCIE1_PF3_AXIST_BYPASS_ENABLED 0 CPM_PCIE1_PF3_AXIST_BYPASS_PREFETCHABLE 0 CPM_PCIE1_PF3_AXIST_BYPASS_SCALE Kilobytes CPM_PCIE1_PF3_AXIST_BYPASS_SIZE 128 CPM_PCIE1_PF3_BAR0_64BIT 0 CPM_PCIE1_PF3_BAR0_ENABLED 1 CPM_PCIE1_PF3_BAR0_PREFETCHABLE 0 CPM_PCIE1_PF3_BAR0_SCALE Ki\
lobytes CPM_PCIE1_PF3_BAR0_SIZE 128 CPM_PCIE1_PF3_BAR0_TYPE Memory CPM_PCIE1_PF3_BAR1_64BIT 0 CPM_PCIE1_PF3_BAR1_ENABLED 0 CPM_PCIE1_PF3_BAR1_PREFETCHABLE 0 CPM_PCIE1_PF3_BAR1_SCALE Kilobytes CPM_PCIE1_PF3_BAR1_SIZE 4 CPM_PCIE1_PF3_BAR1_TYPE Memory CPM_PCIE1_PF3_BAR2_64BIT 0 CPM_PCIE1_PF3_BAR2_ENABLED 0 CPM_PCIE1_PF3_BAR2_PREFETCHABLE 0 CPM_PCIE1_PF3_BAR2_SCALE Kilobytes CPM_PCIE1_PF3_BAR2_SIZE 4 CPM_PCIE1_PF3_BAR2_TYPE Memory CPM_PCIE1_PF3_BAR3_64BIT 0 CPM_PCIE1_PF3_BAR3_ENABLED 0 CPM_PCIE1_PF3\
_BAR3_PREFETCHABLE 0 CPM_PCIE1_PF3_BAR3_SCALE Kilobytes CPM_PCIE1_PF3_BAR3_SIZE 4 CPM_PCIE1_PF3_BAR3_TYPE Memory CPM_PCIE1_PF3_BAR4_64BIT 0 CPM_PCIE1_PF3_BAR4_ENABLED 0 CPM_PCIE1_PF3_BAR4_PREFETCHABLE 0 CPM_PCIE1_PF3_BAR4_SCALE Kilobytes CPM_PCIE1_PF3_BAR4_SIZE 4 CPM_PCIE1_PF3_BAR4_TYPE Memory CPM_PCIE1_PF3_BAR5_64BIT 0 CPM_PCIE1_PF3_BAR5_ENABLED 0 CPM_PCIE1_PF3_BAR5_PREFETCHABLE 0 CPM_PCIE1_PF3_BAR5_SCALE Kilobytes CPM_PCIE1_PF3_BAR5_SIZE 4 CPM_PCIE1_PF3_BAR5_TYPE Memory CPM_PCIE1_PF3_BASE_CLAS\
S_MENU Memory_controller CPM_PCIE1_PF3_BASE_CLASS_VALUE 05 CPM_PCIE1_PF3_CAPABILITY_POINTER 80 CPM_PCIE1_PF3_CFG_DEV_ID B33F CPM_PCIE1_PF3_CFG_REV_ID 0 CPM_PCIE1_PF3_CFG_SUBSYS_ID 7 CPM_PCIE1_PF3_CFG_SUBSYS_VEND_ID 10EE CPM_PCIE1_PF3_CLASS_CODE 0x058000 CPM_PCIE1_PF3_DSN_CAP_ENABLE 0 CPM_PCIE1_PF3_EXPANSION_ROM_ENABLED 0 CPM_PCIE1_PF3_EXPANSION_ROM_SCALE Kilobytes CPM_PCIE1_PF3_EXPANSION_ROM_SIZE 2 CPM_PCIE1_PF3_INTERFACE_VALUE 00 CPM_PCIE1_PF3_INTERRUPT_PIN NONE CPM_PCIE1_PF3_MSIX_CAP_PBA_BIR B\
AR_0 CPM_PCIE1_PF3_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE1_PF3_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE1_PF3_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE1_PF3_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE1_PF3_MSIX_ENABLED 1 CPM_PCIE1_PF3_MSI_CAP_MULTIMSGCAP 1_vector CPM_PCIE1_PF3_MSI_CAP_PERVECMASKCAP 0 CPM_PCIE1_PF3_MSI_ENABLED 1 CPM_PCIE1_PF3_PCIEBAR2AXIBAR_AXIL_MASTER 0x0000000000000000 CPM_PCIE1_PF3_PCIEBAR2AXIBAR_AXIST_BYPASS 0x0000000000000000 CPM_PCIE1_PF3_PRI_CAP_ON 0 CPM_PCIE1_PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED 0 CPM_PCIE1\
_PF3_SRIOV_BAR0_64BIT 0 CPM_PCIE1_PF3_SRIOV_BAR0_ENABLED 1 CPM_PCIE1_PF3_SRIOV_BAR0_PREFETCHABLE 0 CPM_PCIE1_PF3_SRIOV_BAR0_SCALE Kilobytes CPM_PCIE1_PF3_SRIOV_BAR0_SIZE 2 CPM_PCIE1_PF3_SRIOV_BAR0_TYPE Memory CPM_PCIE1_PF3_SRIOV_BAR1_64BIT 0 CPM_PCIE1_PF3_SRIOV_BAR1_ENABLED 0 CPM_PCIE1_PF3_SRIOV_BAR1_PREFETCHABLE 0 CPM_PCIE1_PF3_SRIOV_BAR1_SCALE Kilobytes CPM_PCIE1_PF3_SRIOV_BAR1_SIZE 4 CPM_PCIE1_PF3_SRIOV_BAR1_TYPE Memory CPM_PCIE1_PF3_SRIOV_BAR2_64BIT 0 CPM_PCIE1_PF3_SRIOV_BAR2_ENABLED 0 CPM_P\
CIE1_PF3_SRIOV_BAR2_PREFETCHABLE 0 CPM_PCIE1_PF3_SRIOV_BAR2_SCALE Kilobytes CPM_PCIE1_PF3_SRIOV_BAR2_SIZE 4 CPM_PCIE1_PF3_SRIOV_BAR2_TYPE Memory CPM_PCIE1_PF3_SRIOV_BAR3_64BIT 0 CPM_PCIE1_PF3_SRIOV_BAR3_ENABLED 0 CPM_PCIE1_PF3_SRIOV_BAR3_PREFETCHABLE 0 CPM_PCIE1_PF3_SRIOV_BAR3_SCALE Kilobytes CPM_PCIE1_PF3_SRIOV_BAR3_SIZE 4 CPM_PCIE1_PF3_SRIOV_BAR3_TYPE Memory CPM_PCIE1_PF3_SRIOV_BAR4_64BIT 0 CPM_PCIE1_PF3_SRIOV_BAR4_ENABLED 0 CPM_PCIE1_PF3_SRIOV_BAR4_PREFETCHABLE 0 CPM_PCIE1_PF3_SRIOV_BAR4_SCAL\
E Kilobytes CPM_PCIE1_PF3_SRIOV_BAR4_SIZE 4 CPM_PCIE1_PF3_SRIOV_BAR4_TYPE Memory CPM_PCIE1_PF3_SRIOV_BAR5_64BIT 0 CPM_PCIE1_PF3_SRIOV_BAR5_ENABLED 0 CPM_PCIE1_PF3_SRIOV_BAR5_PREFETCHABLE 0 CPM_PCIE1_PF3_SRIOV_BAR5_SCALE Kilobytes CPM_PCIE1_PF3_SRIOV_BAR5_SIZE 4 CPM_PCIE1_PF3_SRIOV_BAR5_TYPE Memory CPM_PCIE1_PF3_SRIOV_CAP_ENABLE 0 CPM_PCIE1_PF3_SRIOV_CAP_INITIAL_VF 4 CPM_PCIE1_PF3_SRIOV_CAP_TOTAL_VF 0 CPM_PCIE1_PF3_SRIOV_CAP_VER 1 CPM_PCIE1_PF3_SRIOV_FIRST_VF_OFFSET 13 CPM_PCIE1_PF3_SRIOV_FUNC_DE\
P_LINK 0 CPM_PCIE1_PF3_SRIOV_SUPPORTED_PAGE_SIZE 553 CPM_PCIE1_PF3_SRIOV_VF_DEVICE_ID C33F CPM_PCIE1_PF3_SUB_CLASS_INTF_MENU Other_memory_controller CPM_PCIE1_PF3_SUB_CLASS_VALUE 80 CPM_PCIE1_PF3_USE_CLASS_CODE_LOOKUP_ASSISTANT 1 CPM_PCIE1_PF3_VEND_ID 10EE CPM_PCIE1_PFx_MSI_ENABLED 4 CPM_PCIE1_PL_LINK_CAP_MAX_LINK_SPEED Gen3 CPM_PCIE1_PL_LINK_CAP_MAX_LINK_WIDTH NONE CPM_PCIE1_PL_UPSTREAM_FACING 1 CPM_PCIE1_PL_USER_SPARE 0 CPM_PCIE1_PM_ASPML0S_TIMEOUT 0 CPM_PCIE1_PM_ASPML1_ENTRY_DELAY 0 CPM_PCIE1\
_PM_ENABLE_L23_ENTRY 0 CPM_PCIE1_PM_ENABLE_SLOT_POWER_CAPTURE 1 CPM_PCIE1_PM_L1_REENTRY_DELAY 0 CPM_PCIE1_PM_PME_TURNOFF_ACK_DELAY 0 CPM_PCIE1_PORT_TYPE PCI_Express_Endpoint_device CPM_PCIE1_REF_CLK_FREQ 100_MHz CPM_PCIE1_SRIOV_CAP_ENABLE 0 CPM_PCIE1_SRIOV_FIRST_VF_OFFSET 4 CPM_PCIE1_TANDEM None CPM_PCIE1_TL2CFG_IF_PARITY_CHK 0 CPM_PCIE1_TL_NP_FIFO_NUM_TLPS 0 CPM_PCIE1_TL_PF_ENABLE_REG 1 CPM_PCIE1_TL_POSTED_RAM_SIZE 0 CPM_PCIE1_TL_USER_SPARE 0 CPM_PCIE1_TX_FC_IF 0 CPM_PCIE1_TYPE1_MEMBASE_MEMLIMI\
T_ENABLE Disabled CPM_PCIE1_TYPE1_PREFETCHABLE_MEMBASE_MEMLIMIT Disabled CPM_PCIE1_USER_CLK2_FREQ 125_MHz CPM_PCIE1_USER_CLK_FREQ 125_MHz CPM_PCIE1_USER_EDR_CLK2_FREQ 312.5_MHz CPM_PCIE1_USER_EDR_CLK_FREQ 312.5_MHz CPM_PCIE1_VC0_CAPABILITY_POINTER 80 CPM_PCIE1_VC1_BASE_DISABLE 0 CPM_PCIE1_VFG0_ATS_CAP_ON 0 CPM_PCIE1_VFG0_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE1_VFG0_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE1_VFG0_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE1_VFG0_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE1_VFG0_MSIX_CAP_TABLE_SIZE 0\
07 CPM_PCIE1_VFG0_MSIX_ENABLED 1 CPM_PCIE1_VFG0_PRI_CAP_ON 0 CPM_PCIE1_VFG1_ATS_CAP_ON 0 CPM_PCIE1_VFG1_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE1_VFG1_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE1_VFG1_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE1_VFG1_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE1_VFG1_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE1_VFG1_MSIX_ENABLED 1 CPM_PCIE1_VFG1_PRI_CAP_ON 0 CPM_PCIE1_VFG2_ATS_CAP_ON 0 CPM_PCIE1_VFG2_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE1_VFG2_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE1_VFG2_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE1_VFG2\
_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE1_VFG2_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE1_VFG2_MSIX_ENABLED 1 CPM_PCIE1_VFG2_PRI_CAP_ON 0 CPM_PCIE1_VFG3_ATS_CAP_ON 0 CPM_PCIE1_VFG3_MSIX_CAP_PBA_BIR BAR_0 CPM_PCIE1_VFG3_MSIX_CAP_PBA_OFFSET 50 CPM_PCIE1_VFG3_MSIX_CAP_TABLE_BIR BAR_0 CPM_PCIE1_VFG3_MSIX_CAP_TABLE_OFFSET 40 CPM_PCIE1_VFG3_MSIX_CAP_TABLE_SIZE 007 CPM_PCIE1_VFG3_MSIX_ENABLED 1 CPM_PCIE1_VFG3_PRI_CAP_ON 0 CPM_PCIE_CHANNELS_FOR_POWER 0 CPM_PERIPHERAL_EN 0 CPM_PERIPHERAL_TEST_EN 0 CPM_PIPESIM_CLK_MASTE\
R 0 CPM_PIPE_INTF_EN 0 CPM_REQ_AGENTS_0_ENABLE 0 CPM_REQ_AGENTS_0_L2_ENABLE 0 CPM_REQ_AGENTS_1_ENABLE 0 CPM_SELECT_GTOUTCLK TXOUTCLK CPM_SHARE_GTREFCLK 0 CPM_TYPE1_MEMBASE_MEMLIMIT_ENABLE Disabled CPM_TYPE1_PREFETCHABLE_MEMBASE_MEMLIMIT Disabled CPM_USE_MODES None CPM_XDMA_2PF_INTERRUPT_ENABLE 0 CPM_XDMA_TL_PF_VISIBLE 1 CPM_XPIPE_0_CLKDLY_CFG 0 CPM_XPIPE_0_CLK_CFG 0 CPM_XPIPE_0_INSTANTIATED 0 CPM_XPIPE_0_LINK0_CFG DISABLE CPM_XPIPE_0_LINK1_CFG DISABLE CPM_XPIPE_0_LOC QUAD0 CPM_XPIPE_0_MODE 0 CPM\
_XPIPE_0_REG_CFG 0 CPM_XPIPE_0_RSVD 0 CPM_XPIPE_1_CLKDLY_CFG 0 CPM_XPIPE_1_CLK_CFG 0 CPM_XPIPE_1_INSTANTIATED 0 CPM_XPIPE_1_LINK0_CFG DISABLE CPM_XPIPE_1_LINK1_CFG DISABLE CPM_XPIPE_1_LOC QUAD1 CPM_XPIPE_1_MODE 0 CPM_XPIPE_1_REG_CFG 0 CPM_XPIPE_1_RSVD 0 CPM_XPIPE_2_CLKDLY_CFG 0 CPM_XPIPE_2_CLK_CFG 0 CPM_XPIPE_2_INSTANTIATED 0 CPM_XPIPE_2_LINK0_CFG DISABLE CPM_XPIPE_2_LINK1_CFG DISABLE CPM_XPIPE_2_LOC QUAD2 CPM_XPIPE_2_MODE 0 CPM_XPIPE_2_REG_CFG 0 CPM_XPIPE_2_RSVD 0 CPM_XPIPE_3_CLKDLY_CFG 0 CPM_X\
PIPE_3_CLK_CFG 0 CPM_XPIPE_3_INSTANTIATED 0 CPM_XPIPE_3_LINK0_CFG DISABLE CPM_XPIPE_3_LINK1_CFG DISABLE CPM_XPIPE_3_LOC QUAD3 CPM_XPIPE_3_MODE 0 CPM_XPIPE_3_REG_CFG 0 CPM_XPIPE_3_RSVD 0 GT_REFCLK_MHZ 156.25 PMC_REF_CLK_FREQMHZ 33.333 PS_CRL_CPM_TOPSW_REF_CTRL_ACT_FREQMHZ 100 PS_CRL_CPM_TOPSW_REF_CTRL_DIVISOR0 100 PS_CRL_CPM_TOPSW_REF_CTRL_FREQMHZ 100 PS_CRL_CPM_TOPSW_REF_CTRL_SRCSEL PPLL PS_HSDP0_REFCLK 0 PS_HSDP1_REFCLK 0 PS_HSDP_EGRESS_TRAFFIC JTAG PS_HSDP_INGRESS_TRAFFIC JTAG PS_HSDP_MODE NON\
E PS_HSDP_REFCLK_LOC Auto PS_PCIE_RESET_ENABLE 0 PS_PCIE_ROOT_RESET1_IO None PS_PCIE_ROOT_RESET2_IO None PS_USE_NOC_PS_PCI_0 0 PS_USE_PS_NOC_PCI_0 0 PS_USE_PS_NOC_PCI_1 0,XRAM_CONFIG=XRAM_USE_S_AXI_XRAM0 0,XRAM_CONFIG_INTERNAL=XRAM_USE_S_AXI_XRAM0 0,PS_BOARD_INTERFACE=ps_pmc_fixed_io,DESIGN_MODE=1,BOOT_MODE=Custom,CLOCK_MODE=Custom,DDR_MEMORY_MODE=Custom,DDR_MEMORY_MODE_1=Custom,DEBUG_MODE=Custom,IO_CONFIG_MODE=Custom,PS_PL_CONNECTIVITY_MODE=Custom,DEVICE_INTEGRITY_MODE=Custom,preset=None,Compon\
ent_Name=design_1_versal_cips_0_0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* DONT_TOUCH = "true" *)
module design_1_versal_cips_0_0 (
  pl0_ref_clk,
  pl0_resetn,
  fpd_cci_noc_axi0_clk,
  fpd_cci_noc_axi1_clk,
  fpd_cci_noc_axi2_clk,
  fpd_cci_noc_axi3_clk,
  lpd_axi_noc_clk,
  noc_fpd_axi_axi0_clk,
  pmc_axi_noc_axi0_clk,
  gem0_tsu_timer_cnt,
  FPD_CCI_NOC_0_awid,
  FPD_CCI_NOC_0_awaddr,
  FPD_CCI_NOC_0_awlen,
  FPD_CCI_NOC_0_awsize,
  FPD_CCI_NOC_0_awburst,
  FPD_CCI_NOC_0_awlock,
  FPD_CCI_NOC_0_awcache,
  FPD_CCI_NOC_0_awprot,
  FPD_CCI_NOC_0_awvalid,
  FPD_CCI_NOC_0_awuser,
  FPD_CCI_NOC_0_awready,
  FPD_CCI_NOC_0_wdata,
  FPD_CCI_NOC_0_wstrb,
  FPD_CCI_NOC_0_wuser,
  FPD_CCI_NOC_0_wlast,
  FPD_CCI_NOC_0_wvalid,
  FPD_CCI_NOC_0_wready,
  FPD_CCI_NOC_0_bid,
  FPD_CCI_NOC_0_bresp,
  FPD_CCI_NOC_0_bvalid,
  FPD_CCI_NOC_0_bready,
  FPD_CCI_NOC_0_arid,
  FPD_CCI_NOC_0_araddr,
  FPD_CCI_NOC_0_arlen,
  FPD_CCI_NOC_0_arsize,
  FPD_CCI_NOC_0_arburst,
  FPD_CCI_NOC_0_arlock,
  FPD_CCI_NOC_0_arcache,
  FPD_CCI_NOC_0_arprot,
  FPD_CCI_NOC_0_arvalid,
  FPD_CCI_NOC_0_aruser,
  FPD_CCI_NOC_0_arready,
  FPD_CCI_NOC_0_rid,
  FPD_CCI_NOC_0_rdata,
  FPD_CCI_NOC_0_rresp,
  FPD_CCI_NOC_0_rlast,
  FPD_CCI_NOC_0_rvalid,
  FPD_CCI_NOC_0_rready,
  FPD_CCI_NOC_0_awqos,
  FPD_CCI_NOC_0_arqos,
  FPD_CCI_NOC_1_awid,
  FPD_CCI_NOC_1_awaddr,
  FPD_CCI_NOC_1_awlen,
  FPD_CCI_NOC_1_awsize,
  FPD_CCI_NOC_1_awburst,
  FPD_CCI_NOC_1_awlock,
  FPD_CCI_NOC_1_awcache,
  FPD_CCI_NOC_1_awprot,
  FPD_CCI_NOC_1_awvalid,
  FPD_CCI_NOC_1_awuser,
  FPD_CCI_NOC_1_awready,
  FPD_CCI_NOC_1_wdata,
  FPD_CCI_NOC_1_wstrb,
  FPD_CCI_NOC_1_wuser,
  FPD_CCI_NOC_1_wlast,
  FPD_CCI_NOC_1_wvalid,
  FPD_CCI_NOC_1_wready,
  FPD_CCI_NOC_1_bid,
  FPD_CCI_NOC_1_bresp,
  FPD_CCI_NOC_1_bvalid,
  FPD_CCI_NOC_1_bready,
  FPD_CCI_NOC_1_arid,
  FPD_CCI_NOC_1_araddr,
  FPD_CCI_NOC_1_arlen,
  FPD_CCI_NOC_1_arsize,
  FPD_CCI_NOC_1_arburst,
  FPD_CCI_NOC_1_arlock,
  FPD_CCI_NOC_1_arcache,
  FPD_CCI_NOC_1_arprot,
  FPD_CCI_NOC_1_arvalid,
  FPD_CCI_NOC_1_aruser,
  FPD_CCI_NOC_1_arready,
  FPD_CCI_NOC_1_rid,
  FPD_CCI_NOC_1_rdata,
  FPD_CCI_NOC_1_rresp,
  FPD_CCI_NOC_1_rlast,
  FPD_CCI_NOC_1_rvalid,
  FPD_CCI_NOC_1_rready,
  FPD_CCI_NOC_1_awqos,
  FPD_CCI_NOC_1_arqos,
  FPD_CCI_NOC_2_awid,
  FPD_CCI_NOC_2_awaddr,
  FPD_CCI_NOC_2_awlen,
  FPD_CCI_NOC_2_awsize,
  FPD_CCI_NOC_2_awburst,
  FPD_CCI_NOC_2_awlock,
  FPD_CCI_NOC_2_awcache,
  FPD_CCI_NOC_2_awprot,
  FPD_CCI_NOC_2_awvalid,
  FPD_CCI_NOC_2_awuser,
  FPD_CCI_NOC_2_awready,
  FPD_CCI_NOC_2_wdata,
  FPD_CCI_NOC_2_wstrb,
  FPD_CCI_NOC_2_wuser,
  FPD_CCI_NOC_2_wlast,
  FPD_CCI_NOC_2_wvalid,
  FPD_CCI_NOC_2_wready,
  FPD_CCI_NOC_2_bid,
  FPD_CCI_NOC_2_bresp,
  FPD_CCI_NOC_2_bvalid,
  FPD_CCI_NOC_2_bready,
  FPD_CCI_NOC_2_arid,
  FPD_CCI_NOC_2_araddr,
  FPD_CCI_NOC_2_arlen,
  FPD_CCI_NOC_2_arsize,
  FPD_CCI_NOC_2_arburst,
  FPD_CCI_NOC_2_arlock,
  FPD_CCI_NOC_2_arcache,
  FPD_CCI_NOC_2_arprot,
  FPD_CCI_NOC_2_arvalid,
  FPD_CCI_NOC_2_aruser,
  FPD_CCI_NOC_2_arready,
  FPD_CCI_NOC_2_rid,
  FPD_CCI_NOC_2_rdata,
  FPD_CCI_NOC_2_rresp,
  FPD_CCI_NOC_2_rlast,
  FPD_CCI_NOC_2_rvalid,
  FPD_CCI_NOC_2_rready,
  FPD_CCI_NOC_2_awqos,
  FPD_CCI_NOC_2_arqos,
  FPD_CCI_NOC_3_awid,
  FPD_CCI_NOC_3_awaddr,
  FPD_CCI_NOC_3_awlen,
  FPD_CCI_NOC_3_awsize,
  FPD_CCI_NOC_3_awburst,
  FPD_CCI_NOC_3_awlock,
  FPD_CCI_NOC_3_awcache,
  FPD_CCI_NOC_3_awprot,
  FPD_CCI_NOC_3_awvalid,
  FPD_CCI_NOC_3_awuser,
  FPD_CCI_NOC_3_awready,
  FPD_CCI_NOC_3_wdata,
  FPD_CCI_NOC_3_wstrb,
  FPD_CCI_NOC_3_wuser,
  FPD_CCI_NOC_3_wlast,
  FPD_CCI_NOC_3_wvalid,
  FPD_CCI_NOC_3_wready,
  FPD_CCI_NOC_3_bid,
  FPD_CCI_NOC_3_bresp,
  FPD_CCI_NOC_3_bvalid,
  FPD_CCI_NOC_3_bready,
  FPD_CCI_NOC_3_arid,
  FPD_CCI_NOC_3_araddr,
  FPD_CCI_NOC_3_arlen,
  FPD_CCI_NOC_3_arsize,
  FPD_CCI_NOC_3_arburst,
  FPD_CCI_NOC_3_arlock,
  FPD_CCI_NOC_3_arcache,
  FPD_CCI_NOC_3_arprot,
  FPD_CCI_NOC_3_arvalid,
  FPD_CCI_NOC_3_aruser,
  FPD_CCI_NOC_3_arready,
  FPD_CCI_NOC_3_rid,
  FPD_CCI_NOC_3_rdata,
  FPD_CCI_NOC_3_rresp,
  FPD_CCI_NOC_3_rlast,
  FPD_CCI_NOC_3_rvalid,
  FPD_CCI_NOC_3_rready,
  FPD_CCI_NOC_3_awqos,
  FPD_CCI_NOC_3_arqos,
  LPD_AXI_NOC_0_awid,
  LPD_AXI_NOC_0_awaddr,
  LPD_AXI_NOC_0_awlen,
  LPD_AXI_NOC_0_awsize,
  LPD_AXI_NOC_0_awburst,
  LPD_AXI_NOC_0_awlock,
  LPD_AXI_NOC_0_awcache,
  LPD_AXI_NOC_0_awprot,
  LPD_AXI_NOC_0_awvalid,
  LPD_AXI_NOC_0_awuser,
  LPD_AXI_NOC_0_awready,
  LPD_AXI_NOC_0_wdata,
  LPD_AXI_NOC_0_wstrb,
  LPD_AXI_NOC_0_wlast,
  LPD_AXI_NOC_0_wvalid,
  LPD_AXI_NOC_0_wready,
  LPD_AXI_NOC_0_bid,
  LPD_AXI_NOC_0_bresp,
  LPD_AXI_NOC_0_bvalid,
  LPD_AXI_NOC_0_bready,
  LPD_AXI_NOC_0_arid,
  LPD_AXI_NOC_0_araddr,
  LPD_AXI_NOC_0_arlen,
  LPD_AXI_NOC_0_arsize,
  LPD_AXI_NOC_0_arburst,
  LPD_AXI_NOC_0_arlock,
  LPD_AXI_NOC_0_arcache,
  LPD_AXI_NOC_0_arprot,
  LPD_AXI_NOC_0_arvalid,
  LPD_AXI_NOC_0_aruser,
  LPD_AXI_NOC_0_arready,
  LPD_AXI_NOC_0_rid,
  LPD_AXI_NOC_0_rdata,
  LPD_AXI_NOC_0_rresp,
  LPD_AXI_NOC_0_rlast,
  LPD_AXI_NOC_0_rvalid,
  LPD_AXI_NOC_0_rready,
  LPD_AXI_NOC_0_awqos,
  LPD_AXI_NOC_0_arqos,
  NOC_FPD_AXI_0_awaddr,
  NOC_FPD_AXI_0_awlen,
  NOC_FPD_AXI_0_awsize,
  NOC_FPD_AXI_0_awburst,
  NOC_FPD_AXI_0_awlock,
  NOC_FPD_AXI_0_awcache,
  NOC_FPD_AXI_0_awid,
  NOC_FPD_AXI_0_awprot,
  NOC_FPD_AXI_0_awvalid,
  NOC_FPD_AXI_0_bready,
  NOC_FPD_AXI_0_awuser,
  NOC_FPD_AXI_0_wdata,
  NOC_FPD_AXI_0_wid,
  NOC_FPD_AXI_0_wstrb,
  NOC_FPD_AXI_0_wuser,
  NOC_FPD_AXI_0_wlast,
  NOC_FPD_AXI_0_wvalid,
  NOC_FPD_AXI_0_araddr,
  NOC_FPD_AXI_0_arlen,
  NOC_FPD_AXI_0_arsize,
  NOC_FPD_AXI_0_arburst,
  NOC_FPD_AXI_0_arlock,
  NOC_FPD_AXI_0_arcache,
  NOC_FPD_AXI_0_arid,
  NOC_FPD_AXI_0_arprot,
  NOC_FPD_AXI_0_arvalid,
  NOC_FPD_AXI_0_aruser,
  NOC_FPD_AXI_0_rready,
  NOC_FPD_AXI_0_awqos,
  NOC_FPD_AXI_0_awregion,
  NOC_FPD_AXI_0_arqos,
  NOC_FPD_AXI_0_arregion,
  NOC_FPD_AXI_0_arready,
  NOC_FPD_AXI_0_awready,
  NOC_FPD_AXI_0_bid,
  NOC_FPD_AXI_0_bresp,
  NOC_FPD_AXI_0_buser,
  NOC_FPD_AXI_0_bvalid,
  NOC_FPD_AXI_0_rdata,
  NOC_FPD_AXI_0_rid,
  NOC_FPD_AXI_0_rlast,
  NOC_FPD_AXI_0_rresp,
  NOC_FPD_AXI_0_ruser,
  NOC_FPD_AXI_0_rvalid,
  NOC_FPD_AXI_0_wready,
  PMC_NOC_AXI_0_araddr,
  PMC_NOC_AXI_0_arburst,
  PMC_NOC_AXI_0_arcache,
  PMC_NOC_AXI_0_arid,
  PMC_NOC_AXI_0_arlen,
  PMC_NOC_AXI_0_arlock,
  PMC_NOC_AXI_0_arprot,
  PMC_NOC_AXI_0_arqos,
  PMC_NOC_AXI_0_arregion,
  PMC_NOC_AXI_0_arsize,
  PMC_NOC_AXI_0_aruser,
  PMC_NOC_AXI_0_arvalid,
  PMC_NOC_AXI_0_awaddr,
  PMC_NOC_AXI_0_awburst,
  PMC_NOC_AXI_0_awcache,
  PMC_NOC_AXI_0_awid,
  PMC_NOC_AXI_0_awlen,
  PMC_NOC_AXI_0_awlock,
  PMC_NOC_AXI_0_awprot,
  PMC_NOC_AXI_0_awqos,
  PMC_NOC_AXI_0_awregion,
  PMC_NOC_AXI_0_awsize,
  PMC_NOC_AXI_0_awuser,
  PMC_NOC_AXI_0_awvalid,
  PMC_NOC_AXI_0_bready,
  PMC_NOC_AXI_0_rready,
  PMC_NOC_AXI_0_wdata,
  PMC_NOC_AXI_0_wid,
  PMC_NOC_AXI_0_wlast,
  PMC_NOC_AXI_0_wstrb,
  PMC_NOC_AXI_0_wuser,
  PMC_NOC_AXI_0_wvalid,
  PMC_NOC_AXI_0_arready,
  PMC_NOC_AXI_0_awready,
  PMC_NOC_AXI_0_bid,
  PMC_NOC_AXI_0_bresp,
  PMC_NOC_AXI_0_buser,
  PMC_NOC_AXI_0_bvalid,
  PMC_NOC_AXI_0_rdata,
  PMC_NOC_AXI_0_rid,
  PMC_NOC_AXI_0_rlast,
  PMC_NOC_AXI_0_rresp,
  PMC_NOC_AXI_0_ruser,
  PMC_NOC_AXI_0_rvalid,
  PMC_NOC_AXI_0_wready
);

(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.pl0_ref_clk CLK" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.pl0_ref_clk, FREQ_HZ 99999908, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_pl0_ref_clk, INSERT_VIP 0" *)
output wire pl0_ref_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.pl0_resetn RST" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.pl0_resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
output wire pl0_resetn;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.fpd_cci_noc_axi0_clk CLK" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.fpd_cci_noc_axi0_clk, FREQ_HZ 799999268, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi0_clk, ASSOCIATED_BUSIF FPD_CCI_NOC_0, INSERT_VIP 0, PHYSICAL_CHANNEL PS_CCI_TO_NOC_NMU" *)
output wire fpd_cci_noc_axi0_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.fpd_cci_noc_axi1_clk CLK" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.fpd_cci_noc_axi1_clk, FREQ_HZ 799999268, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi1_clk, ASSOCIATED_BUSIF FPD_CCI_NOC_1, INSERT_VIP 0, PHYSICAL_CHANNEL PS_CCI_TO_NOC_NMU" *)
output wire fpd_cci_noc_axi1_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.fpd_cci_noc_axi2_clk CLK" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.fpd_cci_noc_axi2_clk, FREQ_HZ 799999268, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi2_clk, ASSOCIATED_BUSIF FPD_CCI_NOC_2, INSERT_VIP 0, PHYSICAL_CHANNEL PS_CCI_TO_NOC_NMU" *)
output wire fpd_cci_noc_axi2_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.fpd_cci_noc_axi3_clk CLK" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.fpd_cci_noc_axi3_clk, FREQ_HZ 799999268, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi3_clk, ASSOCIATED_BUSIF FPD_CCI_NOC_3, INSERT_VIP 0, PHYSICAL_CHANNEL PS_CCI_TO_NOC_NMU" *)
output wire fpd_cci_noc_axi3_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.lpd_axi_noc_clk CLK" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.lpd_axi_noc_clk, FREQ_HZ 599999451, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_lpd_axi_noc_clk, ASSOCIATED_BUSIF LPD_AXI_NOC_0, INSERT_VIP 0, PHYSICAL_CHANNEL PS_RPU_TO_NOC_NMU" *)
output wire lpd_axi_noc_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.noc_fpd_axi_axi0_clk CLK" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.noc_fpd_axi_axi0_clk, FREQ_HZ 799999268, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_noc_fpd_axi_axi0_clk, ASSOCIATED_BUSIF NOC_FPD_AXI_0, INSERT_VIP 0, PHYSICAL_CHANNEL PS_NCI_TO_NOC_NSU" *)
output wire noc_fpd_axi_axi0_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.pmc_axi_noc_axi0_clk CLK" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.pmc_axi_noc_axi0_clk, FREQ_HZ 400000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_pmc_axi_noc_axi0_clk, ASSOCIATED_BUSIF PMC_NOC_AXI_0, INSERT_VIP 0, PHYSICAL_CHANNEL PS_PMC_TO_NOC_NMU" *)
output wire pmc_axi_noc_axi0_clk;
output wire [93 : 0] gem0_tsu_timer_cnt;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 AWID" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FPD_CCI_NOC_0, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 799999268, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 17, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 64, NUM_WRITE_OUTSTANDING 64, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi0_clk, NUM_REA\
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, CATEGORY noc, MY_CATEGORY ps_cci, PHYSICAL_CHANNEL PS_CCI_TO_NOC_NMU, INDEX 0" *)
output wire [15 : 0] FPD_CCI_NOC_0_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 AWADDR" *)
output wire [63 : 0] FPD_CCI_NOC_0_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 AWLEN" *)
output wire [7 : 0] FPD_CCI_NOC_0_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 AWSIZE" *)
output wire [2 : 0] FPD_CCI_NOC_0_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 AWBURST" *)
output wire [1 : 0] FPD_CCI_NOC_0_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 AWLOCK" *)
output wire FPD_CCI_NOC_0_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 AWCACHE" *)
output wire [3 : 0] FPD_CCI_NOC_0_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 AWPROT" *)
output wire [2 : 0] FPD_CCI_NOC_0_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 AWVALID" *)
output wire FPD_CCI_NOC_0_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 AWUSER" *)
output wire [17 : 0] FPD_CCI_NOC_0_awuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 AWREADY" *)
input wire FPD_CCI_NOC_0_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 WDATA" *)
output wire [127 : 0] FPD_CCI_NOC_0_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 WSTRB" *)
output wire [15 : 0] FPD_CCI_NOC_0_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 WUSER" *)
output wire [16 : 0] FPD_CCI_NOC_0_wuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 WLAST" *)
output wire FPD_CCI_NOC_0_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 WVALID" *)
output wire FPD_CCI_NOC_0_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 WREADY" *)
input wire FPD_CCI_NOC_0_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 BID" *)
input wire [15 : 0] FPD_CCI_NOC_0_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 BRESP" *)
input wire [1 : 0] FPD_CCI_NOC_0_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 BVALID" *)
input wire FPD_CCI_NOC_0_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 BREADY" *)
output wire FPD_CCI_NOC_0_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 ARID" *)
output wire [15 : 0] FPD_CCI_NOC_0_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 ARADDR" *)
output wire [63 : 0] FPD_CCI_NOC_0_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 ARLEN" *)
output wire [7 : 0] FPD_CCI_NOC_0_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 ARSIZE" *)
output wire [2 : 0] FPD_CCI_NOC_0_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 ARBURST" *)
output wire [1 : 0] FPD_CCI_NOC_0_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 ARLOCK" *)
output wire FPD_CCI_NOC_0_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 ARCACHE" *)
output wire [3 : 0] FPD_CCI_NOC_0_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 ARPROT" *)
output wire [2 : 0] FPD_CCI_NOC_0_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 ARVALID" *)
output wire FPD_CCI_NOC_0_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 ARUSER" *)
output wire [17 : 0] FPD_CCI_NOC_0_aruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 ARREADY" *)
input wire FPD_CCI_NOC_0_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 RID" *)
input wire [15 : 0] FPD_CCI_NOC_0_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 RDATA" *)
input wire [127 : 0] FPD_CCI_NOC_0_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 RRESP" *)
input wire [1 : 0] FPD_CCI_NOC_0_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 RLAST" *)
input wire FPD_CCI_NOC_0_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 RVALID" *)
input wire FPD_CCI_NOC_0_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 RREADY" *)
output wire FPD_CCI_NOC_0_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 AWQOS" *)
output wire [3 : 0] FPD_CCI_NOC_0_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_0 ARQOS" *)
output wire [3 : 0] FPD_CCI_NOC_0_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 AWID" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FPD_CCI_NOC_1, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 799999268, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 17, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 64, NUM_WRITE_OUTSTANDING 64, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi1_clk, NUM_REA\
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, CATEGORY noc, MY_CATEGORY ps_cci, PHYSICAL_CHANNEL PS_CCI_TO_NOC_NMU, INDEX 1" *)
output wire [15 : 0] FPD_CCI_NOC_1_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 AWADDR" *)
output wire [63 : 0] FPD_CCI_NOC_1_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 AWLEN" *)
output wire [7 : 0] FPD_CCI_NOC_1_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 AWSIZE" *)
output wire [2 : 0] FPD_CCI_NOC_1_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 AWBURST" *)
output wire [1 : 0] FPD_CCI_NOC_1_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 AWLOCK" *)
output wire FPD_CCI_NOC_1_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 AWCACHE" *)
output wire [3 : 0] FPD_CCI_NOC_1_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 AWPROT" *)
output wire [2 : 0] FPD_CCI_NOC_1_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 AWVALID" *)
output wire FPD_CCI_NOC_1_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 AWUSER" *)
output wire [17 : 0] FPD_CCI_NOC_1_awuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 AWREADY" *)
input wire FPD_CCI_NOC_1_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 WDATA" *)
output wire [127 : 0] FPD_CCI_NOC_1_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 WSTRB" *)
output wire [15 : 0] FPD_CCI_NOC_1_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 WUSER" *)
output wire [16 : 0] FPD_CCI_NOC_1_wuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 WLAST" *)
output wire FPD_CCI_NOC_1_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 WVALID" *)
output wire FPD_CCI_NOC_1_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 WREADY" *)
input wire FPD_CCI_NOC_1_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 BID" *)
input wire [15 : 0] FPD_CCI_NOC_1_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 BRESP" *)
input wire [1 : 0] FPD_CCI_NOC_1_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 BVALID" *)
input wire FPD_CCI_NOC_1_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 BREADY" *)
output wire FPD_CCI_NOC_1_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 ARID" *)
output wire [15 : 0] FPD_CCI_NOC_1_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 ARADDR" *)
output wire [63 : 0] FPD_CCI_NOC_1_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 ARLEN" *)
output wire [7 : 0] FPD_CCI_NOC_1_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 ARSIZE" *)
output wire [2 : 0] FPD_CCI_NOC_1_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 ARBURST" *)
output wire [1 : 0] FPD_CCI_NOC_1_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 ARLOCK" *)
output wire FPD_CCI_NOC_1_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 ARCACHE" *)
output wire [3 : 0] FPD_CCI_NOC_1_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 ARPROT" *)
output wire [2 : 0] FPD_CCI_NOC_1_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 ARVALID" *)
output wire FPD_CCI_NOC_1_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 ARUSER" *)
output wire [17 : 0] FPD_CCI_NOC_1_aruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 ARREADY" *)
input wire FPD_CCI_NOC_1_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 RID" *)
input wire [15 : 0] FPD_CCI_NOC_1_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 RDATA" *)
input wire [127 : 0] FPD_CCI_NOC_1_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 RRESP" *)
input wire [1 : 0] FPD_CCI_NOC_1_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 RLAST" *)
input wire FPD_CCI_NOC_1_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 RVALID" *)
input wire FPD_CCI_NOC_1_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 RREADY" *)
output wire FPD_CCI_NOC_1_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 AWQOS" *)
output wire [3 : 0] FPD_CCI_NOC_1_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_1 ARQOS" *)
output wire [3 : 0] FPD_CCI_NOC_1_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 AWID" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FPD_CCI_NOC_2, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 799999268, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 17, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 64, NUM_WRITE_OUTSTANDING 64, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi2_clk, NUM_REA\
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, CATEGORY noc, MY_CATEGORY ps_cci, PHYSICAL_CHANNEL PS_CCI_TO_NOC_NMU, INDEX 2" *)
output wire [15 : 0] FPD_CCI_NOC_2_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 AWADDR" *)
output wire [63 : 0] FPD_CCI_NOC_2_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 AWLEN" *)
output wire [7 : 0] FPD_CCI_NOC_2_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 AWSIZE" *)
output wire [2 : 0] FPD_CCI_NOC_2_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 AWBURST" *)
output wire [1 : 0] FPD_CCI_NOC_2_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 AWLOCK" *)
output wire FPD_CCI_NOC_2_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 AWCACHE" *)
output wire [3 : 0] FPD_CCI_NOC_2_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 AWPROT" *)
output wire [2 : 0] FPD_CCI_NOC_2_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 AWVALID" *)
output wire FPD_CCI_NOC_2_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 AWUSER" *)
output wire [17 : 0] FPD_CCI_NOC_2_awuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 AWREADY" *)
input wire FPD_CCI_NOC_2_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 WDATA" *)
output wire [127 : 0] FPD_CCI_NOC_2_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 WSTRB" *)
output wire [15 : 0] FPD_CCI_NOC_2_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 WUSER" *)
output wire [16 : 0] FPD_CCI_NOC_2_wuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 WLAST" *)
output wire FPD_CCI_NOC_2_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 WVALID" *)
output wire FPD_CCI_NOC_2_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 WREADY" *)
input wire FPD_CCI_NOC_2_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 BID" *)
input wire [15 : 0] FPD_CCI_NOC_2_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 BRESP" *)
input wire [1 : 0] FPD_CCI_NOC_2_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 BVALID" *)
input wire FPD_CCI_NOC_2_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 BREADY" *)
output wire FPD_CCI_NOC_2_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 ARID" *)
output wire [15 : 0] FPD_CCI_NOC_2_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 ARADDR" *)
output wire [63 : 0] FPD_CCI_NOC_2_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 ARLEN" *)
output wire [7 : 0] FPD_CCI_NOC_2_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 ARSIZE" *)
output wire [2 : 0] FPD_CCI_NOC_2_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 ARBURST" *)
output wire [1 : 0] FPD_CCI_NOC_2_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 ARLOCK" *)
output wire FPD_CCI_NOC_2_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 ARCACHE" *)
output wire [3 : 0] FPD_CCI_NOC_2_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 ARPROT" *)
output wire [2 : 0] FPD_CCI_NOC_2_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 ARVALID" *)
output wire FPD_CCI_NOC_2_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 ARUSER" *)
output wire [17 : 0] FPD_CCI_NOC_2_aruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 ARREADY" *)
input wire FPD_CCI_NOC_2_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 RID" *)
input wire [15 : 0] FPD_CCI_NOC_2_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 RDATA" *)
input wire [127 : 0] FPD_CCI_NOC_2_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 RRESP" *)
input wire [1 : 0] FPD_CCI_NOC_2_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 RLAST" *)
input wire FPD_CCI_NOC_2_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 RVALID" *)
input wire FPD_CCI_NOC_2_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 RREADY" *)
output wire FPD_CCI_NOC_2_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 AWQOS" *)
output wire [3 : 0] FPD_CCI_NOC_2_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_2 ARQOS" *)
output wire [3 : 0] FPD_CCI_NOC_2_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 AWID" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FPD_CCI_NOC_3, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 799999268, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 17, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 64, NUM_WRITE_OUTSTANDING 64, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi3_clk, NUM_REA\
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, CATEGORY noc, MY_CATEGORY ps_cci, PHYSICAL_CHANNEL PS_CCI_TO_NOC_NMU, INDEX 3" *)
output wire [15 : 0] FPD_CCI_NOC_3_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 AWADDR" *)
output wire [63 : 0] FPD_CCI_NOC_3_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 AWLEN" *)
output wire [7 : 0] FPD_CCI_NOC_3_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 AWSIZE" *)
output wire [2 : 0] FPD_CCI_NOC_3_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 AWBURST" *)
output wire [1 : 0] FPD_CCI_NOC_3_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 AWLOCK" *)
output wire FPD_CCI_NOC_3_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 AWCACHE" *)
output wire [3 : 0] FPD_CCI_NOC_3_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 AWPROT" *)
output wire [2 : 0] FPD_CCI_NOC_3_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 AWVALID" *)
output wire FPD_CCI_NOC_3_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 AWUSER" *)
output wire [17 : 0] FPD_CCI_NOC_3_awuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 AWREADY" *)
input wire FPD_CCI_NOC_3_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 WDATA" *)
output wire [127 : 0] FPD_CCI_NOC_3_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 WSTRB" *)
output wire [15 : 0] FPD_CCI_NOC_3_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 WUSER" *)
output wire [16 : 0] FPD_CCI_NOC_3_wuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 WLAST" *)
output wire FPD_CCI_NOC_3_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 WVALID" *)
output wire FPD_CCI_NOC_3_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 WREADY" *)
input wire FPD_CCI_NOC_3_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 BID" *)
input wire [15 : 0] FPD_CCI_NOC_3_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 BRESP" *)
input wire [1 : 0] FPD_CCI_NOC_3_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 BVALID" *)
input wire FPD_CCI_NOC_3_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 BREADY" *)
output wire FPD_CCI_NOC_3_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 ARID" *)
output wire [15 : 0] FPD_CCI_NOC_3_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 ARADDR" *)
output wire [63 : 0] FPD_CCI_NOC_3_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 ARLEN" *)
output wire [7 : 0] FPD_CCI_NOC_3_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 ARSIZE" *)
output wire [2 : 0] FPD_CCI_NOC_3_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 ARBURST" *)
output wire [1 : 0] FPD_CCI_NOC_3_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 ARLOCK" *)
output wire FPD_CCI_NOC_3_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 ARCACHE" *)
output wire [3 : 0] FPD_CCI_NOC_3_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 ARPROT" *)
output wire [2 : 0] FPD_CCI_NOC_3_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 ARVALID" *)
output wire FPD_CCI_NOC_3_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 ARUSER" *)
output wire [17 : 0] FPD_CCI_NOC_3_aruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 ARREADY" *)
input wire FPD_CCI_NOC_3_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 RID" *)
input wire [15 : 0] FPD_CCI_NOC_3_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 RDATA" *)
input wire [127 : 0] FPD_CCI_NOC_3_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 RRESP" *)
input wire [1 : 0] FPD_CCI_NOC_3_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 RLAST" *)
input wire FPD_CCI_NOC_3_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 RVALID" *)
input wire FPD_CCI_NOC_3_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 RREADY" *)
output wire FPD_CCI_NOC_3_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 AWQOS" *)
output wire [3 : 0] FPD_CCI_NOC_3_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 FPD_CCI_NOC_3 ARQOS" *)
output wire [3 : 0] FPD_CCI_NOC_3_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 AWID" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME LPD_AXI_NOC_0, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 599999451, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 64, NUM_WRITE_OUTSTANDING 64, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_lpd_axi_noc_clk, NUM_READ_THRE\
ADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, CATEGORY noc, MY_CATEGORY ps_rpu, PHYSICAL_CHANNEL PS_RPU_TO_NOC_NMU, INDEX 0" *)
output wire [15 : 0] LPD_AXI_NOC_0_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 AWADDR" *)
output wire [63 : 0] LPD_AXI_NOC_0_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 AWLEN" *)
output wire [7 : 0] LPD_AXI_NOC_0_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 AWSIZE" *)
output wire [2 : 0] LPD_AXI_NOC_0_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 AWBURST" *)
output wire [1 : 0] LPD_AXI_NOC_0_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 AWLOCK" *)
output wire LPD_AXI_NOC_0_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 AWCACHE" *)
output wire [3 : 0] LPD_AXI_NOC_0_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 AWPROT" *)
output wire [2 : 0] LPD_AXI_NOC_0_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 AWVALID" *)
output wire LPD_AXI_NOC_0_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 AWUSER" *)
output wire [17 : 0] LPD_AXI_NOC_0_awuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 AWREADY" *)
input wire LPD_AXI_NOC_0_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 WDATA" *)
output wire [127 : 0] LPD_AXI_NOC_0_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 WSTRB" *)
output wire [15 : 0] LPD_AXI_NOC_0_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 WLAST" *)
output wire LPD_AXI_NOC_0_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 WVALID" *)
output wire LPD_AXI_NOC_0_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 WREADY" *)
input wire LPD_AXI_NOC_0_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 BID" *)
input wire [15 : 0] LPD_AXI_NOC_0_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 BRESP" *)
input wire [1 : 0] LPD_AXI_NOC_0_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 BVALID" *)
input wire LPD_AXI_NOC_0_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 BREADY" *)
output wire LPD_AXI_NOC_0_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 ARID" *)
output wire [15 : 0] LPD_AXI_NOC_0_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 ARADDR" *)
output wire [63 : 0] LPD_AXI_NOC_0_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 ARLEN" *)
output wire [7 : 0] LPD_AXI_NOC_0_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 ARSIZE" *)
output wire [2 : 0] LPD_AXI_NOC_0_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 ARBURST" *)
output wire [1 : 0] LPD_AXI_NOC_0_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 ARLOCK" *)
output wire LPD_AXI_NOC_0_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 ARCACHE" *)
output wire [3 : 0] LPD_AXI_NOC_0_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 ARPROT" *)
output wire [2 : 0] LPD_AXI_NOC_0_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 ARVALID" *)
output wire LPD_AXI_NOC_0_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 ARUSER" *)
output wire [17 : 0] LPD_AXI_NOC_0_aruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 ARREADY" *)
input wire LPD_AXI_NOC_0_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 RID" *)
input wire [15 : 0] LPD_AXI_NOC_0_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 RDATA" *)
input wire [127 : 0] LPD_AXI_NOC_0_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 RRESP" *)
input wire [1 : 0] LPD_AXI_NOC_0_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 RLAST" *)
input wire LPD_AXI_NOC_0_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 RVALID" *)
input wire LPD_AXI_NOC_0_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 RREADY" *)
output wire LPD_AXI_NOC_0_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 AWQOS" *)
output wire [3 : 0] LPD_AXI_NOC_0_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 LPD_AXI_NOC_0 ARQOS" *)
output wire [3 : 0] LPD_AXI_NOC_0_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWADDR" *)
(* X_INTERFACE_MODE = "slave" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME NOC_FPD_AXI_0, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 799999268, ID_WIDTH 2, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 17, RUSER_WIDTH 17, BUSER_WIDTH 16, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 32, NUM_WRITE_OUTSTANDING 32, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_noc_fpd_axi_axi0_clk, NUM_RE\
AD_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, CATEGORY noc, MY_CATEGORY ps_nci, PHYSICAL_CHANNEL NOC_NSU_TO_PS_NCI, INDEX 0" *)
input wire [63 : 0] NOC_FPD_AXI_0_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWLEN" *)
input wire [7 : 0] NOC_FPD_AXI_0_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWSIZE" *)
input wire [2 : 0] NOC_FPD_AXI_0_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWBURST" *)
input wire [1 : 0] NOC_FPD_AXI_0_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWLOCK" *)
input wire NOC_FPD_AXI_0_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWCACHE" *)
input wire [3 : 0] NOC_FPD_AXI_0_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWID" *)
input wire [1 : 0] NOC_FPD_AXI_0_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWPROT" *)
input wire [2 : 0] NOC_FPD_AXI_0_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWVALID" *)
input wire NOC_FPD_AXI_0_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 BREADY" *)
input wire NOC_FPD_AXI_0_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWUSER" *)
input wire [17 : 0] NOC_FPD_AXI_0_awuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 WDATA" *)
input wire [127 : 0] NOC_FPD_AXI_0_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 WID" *)
input wire [3 : 0] NOC_FPD_AXI_0_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 WSTRB" *)
input wire [15 : 0] NOC_FPD_AXI_0_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 WUSER" *)
input wire [16 : 0] NOC_FPD_AXI_0_wuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 WLAST" *)
input wire NOC_FPD_AXI_0_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 WVALID" *)
input wire NOC_FPD_AXI_0_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARADDR" *)
input wire [63 : 0] NOC_FPD_AXI_0_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARLEN" *)
input wire [7 : 0] NOC_FPD_AXI_0_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARSIZE" *)
input wire [2 : 0] NOC_FPD_AXI_0_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARBURST" *)
input wire [1 : 0] NOC_FPD_AXI_0_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARLOCK" *)
input wire NOC_FPD_AXI_0_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARCACHE" *)
input wire [3 : 0] NOC_FPD_AXI_0_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARID" *)
input wire [1 : 0] NOC_FPD_AXI_0_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARPROT" *)
input wire [2 : 0] NOC_FPD_AXI_0_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARVALID" *)
input wire NOC_FPD_AXI_0_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARUSER" *)
input wire [17 : 0] NOC_FPD_AXI_0_aruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 RREADY" *)
input wire NOC_FPD_AXI_0_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWQOS" *)
input wire [3 : 0] NOC_FPD_AXI_0_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWREGION" *)
input wire [3 : 0] NOC_FPD_AXI_0_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARQOS" *)
input wire [3 : 0] NOC_FPD_AXI_0_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARREGION" *)
input wire [3 : 0] NOC_FPD_AXI_0_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 ARREADY" *)
output wire NOC_FPD_AXI_0_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 AWREADY" *)
output wire NOC_FPD_AXI_0_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 BID" *)
output wire [1 : 0] NOC_FPD_AXI_0_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 BRESP" *)
output wire [1 : 0] NOC_FPD_AXI_0_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 BUSER" *)
output wire [15 : 0] NOC_FPD_AXI_0_buser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 BVALID" *)
output wire NOC_FPD_AXI_0_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 RDATA" *)
output wire [127 : 0] NOC_FPD_AXI_0_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 RID" *)
output wire [1 : 0] NOC_FPD_AXI_0_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 RLAST" *)
output wire NOC_FPD_AXI_0_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 RRESP" *)
output wire [1 : 0] NOC_FPD_AXI_0_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 RUSER" *)
output wire [16 : 0] NOC_FPD_AXI_0_ruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 RVALID" *)
output wire NOC_FPD_AXI_0_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 NOC_FPD_AXI_0 WREADY" *)
output wire NOC_FPD_AXI_0_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARADDR" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PMC_NOC_AXI_0, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 400000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 17, RUSER_WIDTH 17, BUSER_WIDTH 16, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 64, NUM_WRITE_OUTSTANDING 64, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_pmc_axi_noc_axi0_clk, NUM_R\
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, CATEGORY noc, MY_CATEGORY ps_pmc, PHYSICAL_CHANNEL PS_PMC_TO_NOC_NMU, HD_TANDEM 0, INDEX 0, SLR_INDEX 0" *)
output wire [63 : 0] PMC_NOC_AXI_0_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARBURST" *)
output wire [1 : 0] PMC_NOC_AXI_0_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARCACHE" *)
output wire [3 : 0] PMC_NOC_AXI_0_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARID" *)
output wire [15 : 0] PMC_NOC_AXI_0_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARLEN" *)
output wire [7 : 0] PMC_NOC_AXI_0_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARLOCK" *)
output wire PMC_NOC_AXI_0_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARPROT" *)
output wire [2 : 0] PMC_NOC_AXI_0_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARQOS" *)
output wire [3 : 0] PMC_NOC_AXI_0_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARREGION" *)
output wire [3 : 0] PMC_NOC_AXI_0_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARSIZE" *)
output wire [2 : 0] PMC_NOC_AXI_0_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARUSER" *)
output wire [17 : 0] PMC_NOC_AXI_0_aruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARVALID" *)
output wire PMC_NOC_AXI_0_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWADDR" *)
output wire [63 : 0] PMC_NOC_AXI_0_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWBURST" *)
output wire [1 : 0] PMC_NOC_AXI_0_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWCACHE" *)
output wire [3 : 0] PMC_NOC_AXI_0_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWID" *)
output wire [15 : 0] PMC_NOC_AXI_0_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWLEN" *)
output wire [7 : 0] PMC_NOC_AXI_0_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWLOCK" *)
output wire PMC_NOC_AXI_0_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWPROT" *)
output wire [2 : 0] PMC_NOC_AXI_0_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWQOS" *)
output wire [3 : 0] PMC_NOC_AXI_0_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWREGION" *)
output wire [3 : 0] PMC_NOC_AXI_0_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWSIZE" *)
output wire [2 : 0] PMC_NOC_AXI_0_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWUSER" *)
output wire [17 : 0] PMC_NOC_AXI_0_awuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWVALID" *)
output wire PMC_NOC_AXI_0_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 BREADY" *)
output wire PMC_NOC_AXI_0_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 RREADY" *)
output wire PMC_NOC_AXI_0_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 WDATA" *)
output wire [127 : 0] PMC_NOC_AXI_0_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 WID" *)
output wire [15 : 0] PMC_NOC_AXI_0_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 WLAST" *)
output wire PMC_NOC_AXI_0_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 WSTRB" *)
output wire [15 : 0] PMC_NOC_AXI_0_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 WUSER" *)
output wire [16 : 0] PMC_NOC_AXI_0_wuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 WVALID" *)
output wire PMC_NOC_AXI_0_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 ARREADY" *)
input wire PMC_NOC_AXI_0_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 AWREADY" *)
input wire PMC_NOC_AXI_0_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 BID" *)
input wire [15 : 0] PMC_NOC_AXI_0_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 BRESP" *)
input wire [1 : 0] PMC_NOC_AXI_0_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 BUSER" *)
input wire [15 : 0] PMC_NOC_AXI_0_buser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 BVALID" *)
input wire PMC_NOC_AXI_0_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 RDATA" *)
input wire [127 : 0] PMC_NOC_AXI_0_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 RID" *)
input wire [15 : 0] PMC_NOC_AXI_0_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 RLAST" *)
input wire PMC_NOC_AXI_0_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 RRESP" *)
input wire [1 : 0] PMC_NOC_AXI_0_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 RUSER" *)
input wire [16 : 0] PMC_NOC_AXI_0_ruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 RVALID" *)
input wire PMC_NOC_AXI_0_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PMC_NOC_AXI_0 WREADY" *)
input wire PMC_NOC_AXI_0_wready;

  bd_70da inst (
    .pl0_ref_clk(pl0_ref_clk),
    .pl0_resetn(pl0_resetn),
    .fpd_cci_noc_axi0_clk(fpd_cci_noc_axi0_clk),
    .fpd_cci_noc_axi1_clk(fpd_cci_noc_axi1_clk),
    .fpd_cci_noc_axi2_clk(fpd_cci_noc_axi2_clk),
    .fpd_cci_noc_axi3_clk(fpd_cci_noc_axi3_clk),
    .lpd_axi_noc_clk(lpd_axi_noc_clk),
    .noc_fpd_axi_axi0_clk(noc_fpd_axi_axi0_clk),
    .pmc_axi_noc_axi0_clk(pmc_axi_noc_axi0_clk),
    .gem0_tsu_timer_cnt(gem0_tsu_timer_cnt),
    .FPD_CCI_NOC_0_awid(FPD_CCI_NOC_0_awid),
    .FPD_CCI_NOC_0_awaddr(FPD_CCI_NOC_0_awaddr),
    .FPD_CCI_NOC_0_awlen(FPD_CCI_NOC_0_awlen),
    .FPD_CCI_NOC_0_awsize(FPD_CCI_NOC_0_awsize),
    .FPD_CCI_NOC_0_awburst(FPD_CCI_NOC_0_awburst),
    .FPD_CCI_NOC_0_awlock(FPD_CCI_NOC_0_awlock),
    .FPD_CCI_NOC_0_awcache(FPD_CCI_NOC_0_awcache),
    .FPD_CCI_NOC_0_awprot(FPD_CCI_NOC_0_awprot),
    .FPD_CCI_NOC_0_awvalid(FPD_CCI_NOC_0_awvalid),
    .FPD_CCI_NOC_0_awuser(FPD_CCI_NOC_0_awuser),
    .FPD_CCI_NOC_0_awready(FPD_CCI_NOC_0_awready),
    .FPD_CCI_NOC_0_wdata(FPD_CCI_NOC_0_wdata),
    .FPD_CCI_NOC_0_wstrb(FPD_CCI_NOC_0_wstrb),
    .FPD_CCI_NOC_0_wuser(FPD_CCI_NOC_0_wuser),
    .FPD_CCI_NOC_0_wlast(FPD_CCI_NOC_0_wlast),
    .FPD_CCI_NOC_0_wvalid(FPD_CCI_NOC_0_wvalid),
    .FPD_CCI_NOC_0_wready(FPD_CCI_NOC_0_wready),
    .FPD_CCI_NOC_0_bid(FPD_CCI_NOC_0_bid),
    .FPD_CCI_NOC_0_bresp(FPD_CCI_NOC_0_bresp),
    .FPD_CCI_NOC_0_bvalid(FPD_CCI_NOC_0_bvalid),
    .FPD_CCI_NOC_0_bready(FPD_CCI_NOC_0_bready),
    .FPD_CCI_NOC_0_arid(FPD_CCI_NOC_0_arid),
    .FPD_CCI_NOC_0_araddr(FPD_CCI_NOC_0_araddr),
    .FPD_CCI_NOC_0_arlen(FPD_CCI_NOC_0_arlen),
    .FPD_CCI_NOC_0_arsize(FPD_CCI_NOC_0_arsize),
    .FPD_CCI_NOC_0_arburst(FPD_CCI_NOC_0_arburst),
    .FPD_CCI_NOC_0_arlock(FPD_CCI_NOC_0_arlock),
    .FPD_CCI_NOC_0_arcache(FPD_CCI_NOC_0_arcache),
    .FPD_CCI_NOC_0_arprot(FPD_CCI_NOC_0_arprot),
    .FPD_CCI_NOC_0_arvalid(FPD_CCI_NOC_0_arvalid),
    .FPD_CCI_NOC_0_aruser(FPD_CCI_NOC_0_aruser),
    .FPD_CCI_NOC_0_arready(FPD_CCI_NOC_0_arready),
    .FPD_CCI_NOC_0_rid(FPD_CCI_NOC_0_rid),
    .FPD_CCI_NOC_0_rdata(FPD_CCI_NOC_0_rdata),
    .FPD_CCI_NOC_0_rresp(FPD_CCI_NOC_0_rresp),
    .FPD_CCI_NOC_0_rlast(FPD_CCI_NOC_0_rlast),
    .FPD_CCI_NOC_0_rvalid(FPD_CCI_NOC_0_rvalid),
    .FPD_CCI_NOC_0_rready(FPD_CCI_NOC_0_rready),
    .FPD_CCI_NOC_0_awqos(FPD_CCI_NOC_0_awqos),
    .FPD_CCI_NOC_0_arqos(FPD_CCI_NOC_0_arqos),
    .FPD_CCI_NOC_1_awid(FPD_CCI_NOC_1_awid),
    .FPD_CCI_NOC_1_awaddr(FPD_CCI_NOC_1_awaddr),
    .FPD_CCI_NOC_1_awlen(FPD_CCI_NOC_1_awlen),
    .FPD_CCI_NOC_1_awsize(FPD_CCI_NOC_1_awsize),
    .FPD_CCI_NOC_1_awburst(FPD_CCI_NOC_1_awburst),
    .FPD_CCI_NOC_1_awlock(FPD_CCI_NOC_1_awlock),
    .FPD_CCI_NOC_1_awcache(FPD_CCI_NOC_1_awcache),
    .FPD_CCI_NOC_1_awprot(FPD_CCI_NOC_1_awprot),
    .FPD_CCI_NOC_1_awvalid(FPD_CCI_NOC_1_awvalid),
    .FPD_CCI_NOC_1_awuser(FPD_CCI_NOC_1_awuser),
    .FPD_CCI_NOC_1_awready(FPD_CCI_NOC_1_awready),
    .FPD_CCI_NOC_1_wdata(FPD_CCI_NOC_1_wdata),
    .FPD_CCI_NOC_1_wstrb(FPD_CCI_NOC_1_wstrb),
    .FPD_CCI_NOC_1_wuser(FPD_CCI_NOC_1_wuser),
    .FPD_CCI_NOC_1_wlast(FPD_CCI_NOC_1_wlast),
    .FPD_CCI_NOC_1_wvalid(FPD_CCI_NOC_1_wvalid),
    .FPD_CCI_NOC_1_wready(FPD_CCI_NOC_1_wready),
    .FPD_CCI_NOC_1_bid(FPD_CCI_NOC_1_bid),
    .FPD_CCI_NOC_1_bresp(FPD_CCI_NOC_1_bresp),
    .FPD_CCI_NOC_1_bvalid(FPD_CCI_NOC_1_bvalid),
    .FPD_CCI_NOC_1_bready(FPD_CCI_NOC_1_bready),
    .FPD_CCI_NOC_1_arid(FPD_CCI_NOC_1_arid),
    .FPD_CCI_NOC_1_araddr(FPD_CCI_NOC_1_araddr),
    .FPD_CCI_NOC_1_arlen(FPD_CCI_NOC_1_arlen),
    .FPD_CCI_NOC_1_arsize(FPD_CCI_NOC_1_arsize),
    .FPD_CCI_NOC_1_arburst(FPD_CCI_NOC_1_arburst),
    .FPD_CCI_NOC_1_arlock(FPD_CCI_NOC_1_arlock),
    .FPD_CCI_NOC_1_arcache(FPD_CCI_NOC_1_arcache),
    .FPD_CCI_NOC_1_arprot(FPD_CCI_NOC_1_arprot),
    .FPD_CCI_NOC_1_arvalid(FPD_CCI_NOC_1_arvalid),
    .FPD_CCI_NOC_1_aruser(FPD_CCI_NOC_1_aruser),
    .FPD_CCI_NOC_1_arready(FPD_CCI_NOC_1_arready),
    .FPD_CCI_NOC_1_rid(FPD_CCI_NOC_1_rid),
    .FPD_CCI_NOC_1_rdata(FPD_CCI_NOC_1_rdata),
    .FPD_CCI_NOC_1_rresp(FPD_CCI_NOC_1_rresp),
    .FPD_CCI_NOC_1_rlast(FPD_CCI_NOC_1_rlast),
    .FPD_CCI_NOC_1_rvalid(FPD_CCI_NOC_1_rvalid),
    .FPD_CCI_NOC_1_rready(FPD_CCI_NOC_1_rready),
    .FPD_CCI_NOC_1_awqos(FPD_CCI_NOC_1_awqos),
    .FPD_CCI_NOC_1_arqos(FPD_CCI_NOC_1_arqos),
    .FPD_CCI_NOC_2_awid(FPD_CCI_NOC_2_awid),
    .FPD_CCI_NOC_2_awaddr(FPD_CCI_NOC_2_awaddr),
    .FPD_CCI_NOC_2_awlen(FPD_CCI_NOC_2_awlen),
    .FPD_CCI_NOC_2_awsize(FPD_CCI_NOC_2_awsize),
    .FPD_CCI_NOC_2_awburst(FPD_CCI_NOC_2_awburst),
    .FPD_CCI_NOC_2_awlock(FPD_CCI_NOC_2_awlock),
    .FPD_CCI_NOC_2_awcache(FPD_CCI_NOC_2_awcache),
    .FPD_CCI_NOC_2_awprot(FPD_CCI_NOC_2_awprot),
    .FPD_CCI_NOC_2_awvalid(FPD_CCI_NOC_2_awvalid),
    .FPD_CCI_NOC_2_awuser(FPD_CCI_NOC_2_awuser),
    .FPD_CCI_NOC_2_awready(FPD_CCI_NOC_2_awready),
    .FPD_CCI_NOC_2_wdata(FPD_CCI_NOC_2_wdata),
    .FPD_CCI_NOC_2_wstrb(FPD_CCI_NOC_2_wstrb),
    .FPD_CCI_NOC_2_wuser(FPD_CCI_NOC_2_wuser),
    .FPD_CCI_NOC_2_wlast(FPD_CCI_NOC_2_wlast),
    .FPD_CCI_NOC_2_wvalid(FPD_CCI_NOC_2_wvalid),
    .FPD_CCI_NOC_2_wready(FPD_CCI_NOC_2_wready),
    .FPD_CCI_NOC_2_bid(FPD_CCI_NOC_2_bid),
    .FPD_CCI_NOC_2_bresp(FPD_CCI_NOC_2_bresp),
    .FPD_CCI_NOC_2_bvalid(FPD_CCI_NOC_2_bvalid),
    .FPD_CCI_NOC_2_bready(FPD_CCI_NOC_2_bready),
    .FPD_CCI_NOC_2_arid(FPD_CCI_NOC_2_arid),
    .FPD_CCI_NOC_2_araddr(FPD_CCI_NOC_2_araddr),
    .FPD_CCI_NOC_2_arlen(FPD_CCI_NOC_2_arlen),
    .FPD_CCI_NOC_2_arsize(FPD_CCI_NOC_2_arsize),
    .FPD_CCI_NOC_2_arburst(FPD_CCI_NOC_2_arburst),
    .FPD_CCI_NOC_2_arlock(FPD_CCI_NOC_2_arlock),
    .FPD_CCI_NOC_2_arcache(FPD_CCI_NOC_2_arcache),
    .FPD_CCI_NOC_2_arprot(FPD_CCI_NOC_2_arprot),
    .FPD_CCI_NOC_2_arvalid(FPD_CCI_NOC_2_arvalid),
    .FPD_CCI_NOC_2_aruser(FPD_CCI_NOC_2_aruser),
    .FPD_CCI_NOC_2_arready(FPD_CCI_NOC_2_arready),
    .FPD_CCI_NOC_2_rid(FPD_CCI_NOC_2_rid),
    .FPD_CCI_NOC_2_rdata(FPD_CCI_NOC_2_rdata),
    .FPD_CCI_NOC_2_rresp(FPD_CCI_NOC_2_rresp),
    .FPD_CCI_NOC_2_rlast(FPD_CCI_NOC_2_rlast),
    .FPD_CCI_NOC_2_rvalid(FPD_CCI_NOC_2_rvalid),
    .FPD_CCI_NOC_2_rready(FPD_CCI_NOC_2_rready),
    .FPD_CCI_NOC_2_awqos(FPD_CCI_NOC_2_awqos),
    .FPD_CCI_NOC_2_arqos(FPD_CCI_NOC_2_arqos),
    .FPD_CCI_NOC_3_awid(FPD_CCI_NOC_3_awid),
    .FPD_CCI_NOC_3_awaddr(FPD_CCI_NOC_3_awaddr),
    .FPD_CCI_NOC_3_awlen(FPD_CCI_NOC_3_awlen),
    .FPD_CCI_NOC_3_awsize(FPD_CCI_NOC_3_awsize),
    .FPD_CCI_NOC_3_awburst(FPD_CCI_NOC_3_awburst),
    .FPD_CCI_NOC_3_awlock(FPD_CCI_NOC_3_awlock),
    .FPD_CCI_NOC_3_awcache(FPD_CCI_NOC_3_awcache),
    .FPD_CCI_NOC_3_awprot(FPD_CCI_NOC_3_awprot),
    .FPD_CCI_NOC_3_awvalid(FPD_CCI_NOC_3_awvalid),
    .FPD_CCI_NOC_3_awuser(FPD_CCI_NOC_3_awuser),
    .FPD_CCI_NOC_3_awready(FPD_CCI_NOC_3_awready),
    .FPD_CCI_NOC_3_wdata(FPD_CCI_NOC_3_wdata),
    .FPD_CCI_NOC_3_wstrb(FPD_CCI_NOC_3_wstrb),
    .FPD_CCI_NOC_3_wuser(FPD_CCI_NOC_3_wuser),
    .FPD_CCI_NOC_3_wlast(FPD_CCI_NOC_3_wlast),
    .FPD_CCI_NOC_3_wvalid(FPD_CCI_NOC_3_wvalid),
    .FPD_CCI_NOC_3_wready(FPD_CCI_NOC_3_wready),
    .FPD_CCI_NOC_3_bid(FPD_CCI_NOC_3_bid),
    .FPD_CCI_NOC_3_bresp(FPD_CCI_NOC_3_bresp),
    .FPD_CCI_NOC_3_bvalid(FPD_CCI_NOC_3_bvalid),
    .FPD_CCI_NOC_3_bready(FPD_CCI_NOC_3_bready),
    .FPD_CCI_NOC_3_arid(FPD_CCI_NOC_3_arid),
    .FPD_CCI_NOC_3_araddr(FPD_CCI_NOC_3_araddr),
    .FPD_CCI_NOC_3_arlen(FPD_CCI_NOC_3_arlen),
    .FPD_CCI_NOC_3_arsize(FPD_CCI_NOC_3_arsize),
    .FPD_CCI_NOC_3_arburst(FPD_CCI_NOC_3_arburst),
    .FPD_CCI_NOC_3_arlock(FPD_CCI_NOC_3_arlock),
    .FPD_CCI_NOC_3_arcache(FPD_CCI_NOC_3_arcache),
    .FPD_CCI_NOC_3_arprot(FPD_CCI_NOC_3_arprot),
    .FPD_CCI_NOC_3_arvalid(FPD_CCI_NOC_3_arvalid),
    .FPD_CCI_NOC_3_aruser(FPD_CCI_NOC_3_aruser),
    .FPD_CCI_NOC_3_arready(FPD_CCI_NOC_3_arready),
    .FPD_CCI_NOC_3_rid(FPD_CCI_NOC_3_rid),
    .FPD_CCI_NOC_3_rdata(FPD_CCI_NOC_3_rdata),
    .FPD_CCI_NOC_3_rresp(FPD_CCI_NOC_3_rresp),
    .FPD_CCI_NOC_3_rlast(FPD_CCI_NOC_3_rlast),
    .FPD_CCI_NOC_3_rvalid(FPD_CCI_NOC_3_rvalid),
    .FPD_CCI_NOC_3_rready(FPD_CCI_NOC_3_rready),
    .FPD_CCI_NOC_3_awqos(FPD_CCI_NOC_3_awqos),
    .FPD_CCI_NOC_3_arqos(FPD_CCI_NOC_3_arqos),
    .LPD_AXI_NOC_0_awid(LPD_AXI_NOC_0_awid),
    .LPD_AXI_NOC_0_awaddr(LPD_AXI_NOC_0_awaddr),
    .LPD_AXI_NOC_0_awlen(LPD_AXI_NOC_0_awlen),
    .LPD_AXI_NOC_0_awsize(LPD_AXI_NOC_0_awsize),
    .LPD_AXI_NOC_0_awburst(LPD_AXI_NOC_0_awburst),
    .LPD_AXI_NOC_0_awlock(LPD_AXI_NOC_0_awlock),
    .LPD_AXI_NOC_0_awcache(LPD_AXI_NOC_0_awcache),
    .LPD_AXI_NOC_0_awprot(LPD_AXI_NOC_0_awprot),
    .LPD_AXI_NOC_0_awvalid(LPD_AXI_NOC_0_awvalid),
    .LPD_AXI_NOC_0_awuser(LPD_AXI_NOC_0_awuser),
    .LPD_AXI_NOC_0_awready(LPD_AXI_NOC_0_awready),
    .LPD_AXI_NOC_0_wdata(LPD_AXI_NOC_0_wdata),
    .LPD_AXI_NOC_0_wstrb(LPD_AXI_NOC_0_wstrb),
    .LPD_AXI_NOC_0_wlast(LPD_AXI_NOC_0_wlast),
    .LPD_AXI_NOC_0_wvalid(LPD_AXI_NOC_0_wvalid),
    .LPD_AXI_NOC_0_wready(LPD_AXI_NOC_0_wready),
    .LPD_AXI_NOC_0_bid(LPD_AXI_NOC_0_bid),
    .LPD_AXI_NOC_0_bresp(LPD_AXI_NOC_0_bresp),
    .LPD_AXI_NOC_0_bvalid(LPD_AXI_NOC_0_bvalid),
    .LPD_AXI_NOC_0_bready(LPD_AXI_NOC_0_bready),
    .LPD_AXI_NOC_0_arid(LPD_AXI_NOC_0_arid),
    .LPD_AXI_NOC_0_araddr(LPD_AXI_NOC_0_araddr),
    .LPD_AXI_NOC_0_arlen(LPD_AXI_NOC_0_arlen),
    .LPD_AXI_NOC_0_arsize(LPD_AXI_NOC_0_arsize),
    .LPD_AXI_NOC_0_arburst(LPD_AXI_NOC_0_arburst),
    .LPD_AXI_NOC_0_arlock(LPD_AXI_NOC_0_arlock),
    .LPD_AXI_NOC_0_arcache(LPD_AXI_NOC_0_arcache),
    .LPD_AXI_NOC_0_arprot(LPD_AXI_NOC_0_arprot),
    .LPD_AXI_NOC_0_arvalid(LPD_AXI_NOC_0_arvalid),
    .LPD_AXI_NOC_0_aruser(LPD_AXI_NOC_0_aruser),
    .LPD_AXI_NOC_0_arready(LPD_AXI_NOC_0_arready),
    .LPD_AXI_NOC_0_rid(LPD_AXI_NOC_0_rid),
    .LPD_AXI_NOC_0_rdata(LPD_AXI_NOC_0_rdata),
    .LPD_AXI_NOC_0_rresp(LPD_AXI_NOC_0_rresp),
    .LPD_AXI_NOC_0_rlast(LPD_AXI_NOC_0_rlast),
    .LPD_AXI_NOC_0_rvalid(LPD_AXI_NOC_0_rvalid),
    .LPD_AXI_NOC_0_rready(LPD_AXI_NOC_0_rready),
    .LPD_AXI_NOC_0_awqos(LPD_AXI_NOC_0_awqos),
    .LPD_AXI_NOC_0_arqos(LPD_AXI_NOC_0_arqos),
    .NOC_FPD_AXI_0_awaddr(NOC_FPD_AXI_0_awaddr),
    .NOC_FPD_AXI_0_awlen(NOC_FPD_AXI_0_awlen),
    .NOC_FPD_AXI_0_awsize(NOC_FPD_AXI_0_awsize),
    .NOC_FPD_AXI_0_awburst(NOC_FPD_AXI_0_awburst),
    .NOC_FPD_AXI_0_awlock(NOC_FPD_AXI_0_awlock),
    .NOC_FPD_AXI_0_awcache(NOC_FPD_AXI_0_awcache),
    .NOC_FPD_AXI_0_awid(NOC_FPD_AXI_0_awid),
    .NOC_FPD_AXI_0_awprot(NOC_FPD_AXI_0_awprot),
    .NOC_FPD_AXI_0_awvalid(NOC_FPD_AXI_0_awvalid),
    .NOC_FPD_AXI_0_bready(NOC_FPD_AXI_0_bready),
    .NOC_FPD_AXI_0_awuser(NOC_FPD_AXI_0_awuser),
    .NOC_FPD_AXI_0_wdata(NOC_FPD_AXI_0_wdata),
    .NOC_FPD_AXI_0_wid(NOC_FPD_AXI_0_wid),
    .NOC_FPD_AXI_0_wstrb(NOC_FPD_AXI_0_wstrb),
    .NOC_FPD_AXI_0_wuser(NOC_FPD_AXI_0_wuser),
    .NOC_FPD_AXI_0_wlast(NOC_FPD_AXI_0_wlast),
    .NOC_FPD_AXI_0_wvalid(NOC_FPD_AXI_0_wvalid),
    .NOC_FPD_AXI_0_araddr(NOC_FPD_AXI_0_araddr),
    .NOC_FPD_AXI_0_arlen(NOC_FPD_AXI_0_arlen),
    .NOC_FPD_AXI_0_arsize(NOC_FPD_AXI_0_arsize),
    .NOC_FPD_AXI_0_arburst(NOC_FPD_AXI_0_arburst),
    .NOC_FPD_AXI_0_arlock(NOC_FPD_AXI_0_arlock),
    .NOC_FPD_AXI_0_arcache(NOC_FPD_AXI_0_arcache),
    .NOC_FPD_AXI_0_arid(NOC_FPD_AXI_0_arid),
    .NOC_FPD_AXI_0_arprot(NOC_FPD_AXI_0_arprot),
    .NOC_FPD_AXI_0_arvalid(NOC_FPD_AXI_0_arvalid),
    .NOC_FPD_AXI_0_aruser(NOC_FPD_AXI_0_aruser),
    .NOC_FPD_AXI_0_rready(NOC_FPD_AXI_0_rready),
    .NOC_FPD_AXI_0_awqos(NOC_FPD_AXI_0_awqos),
    .NOC_FPD_AXI_0_awregion(NOC_FPD_AXI_0_awregion),
    .NOC_FPD_AXI_0_arqos(NOC_FPD_AXI_0_arqos),
    .NOC_FPD_AXI_0_arregion(NOC_FPD_AXI_0_arregion),
    .NOC_FPD_AXI_0_arready(NOC_FPD_AXI_0_arready),
    .NOC_FPD_AXI_0_awready(NOC_FPD_AXI_0_awready),
    .NOC_FPD_AXI_0_bid(NOC_FPD_AXI_0_bid),
    .NOC_FPD_AXI_0_bresp(NOC_FPD_AXI_0_bresp),
    .NOC_FPD_AXI_0_buser(NOC_FPD_AXI_0_buser),
    .NOC_FPD_AXI_0_bvalid(NOC_FPD_AXI_0_bvalid),
    .NOC_FPD_AXI_0_rdata(NOC_FPD_AXI_0_rdata),
    .NOC_FPD_AXI_0_rid(NOC_FPD_AXI_0_rid),
    .NOC_FPD_AXI_0_rlast(NOC_FPD_AXI_0_rlast),
    .NOC_FPD_AXI_0_rresp(NOC_FPD_AXI_0_rresp),
    .NOC_FPD_AXI_0_ruser(NOC_FPD_AXI_0_ruser),
    .NOC_FPD_AXI_0_rvalid(NOC_FPD_AXI_0_rvalid),
    .NOC_FPD_AXI_0_wready(NOC_FPD_AXI_0_wready),
    .PMC_NOC_AXI_0_araddr(PMC_NOC_AXI_0_araddr),
    .PMC_NOC_AXI_0_arburst(PMC_NOC_AXI_0_arburst),
    .PMC_NOC_AXI_0_arcache(PMC_NOC_AXI_0_arcache),
    .PMC_NOC_AXI_0_arid(PMC_NOC_AXI_0_arid),
    .PMC_NOC_AXI_0_arlen(PMC_NOC_AXI_0_arlen),
    .PMC_NOC_AXI_0_arlock(PMC_NOC_AXI_0_arlock),
    .PMC_NOC_AXI_0_arprot(PMC_NOC_AXI_0_arprot),
    .PMC_NOC_AXI_0_arqos(PMC_NOC_AXI_0_arqos),
    .PMC_NOC_AXI_0_arregion(PMC_NOC_AXI_0_arregion),
    .PMC_NOC_AXI_0_arsize(PMC_NOC_AXI_0_arsize),
    .PMC_NOC_AXI_0_aruser(PMC_NOC_AXI_0_aruser),
    .PMC_NOC_AXI_0_arvalid(PMC_NOC_AXI_0_arvalid),
    .PMC_NOC_AXI_0_awaddr(PMC_NOC_AXI_0_awaddr),
    .PMC_NOC_AXI_0_awburst(PMC_NOC_AXI_0_awburst),
    .PMC_NOC_AXI_0_awcache(PMC_NOC_AXI_0_awcache),
    .PMC_NOC_AXI_0_awid(PMC_NOC_AXI_0_awid),
    .PMC_NOC_AXI_0_awlen(PMC_NOC_AXI_0_awlen),
    .PMC_NOC_AXI_0_awlock(PMC_NOC_AXI_0_awlock),
    .PMC_NOC_AXI_0_awprot(PMC_NOC_AXI_0_awprot),
    .PMC_NOC_AXI_0_awqos(PMC_NOC_AXI_0_awqos),
    .PMC_NOC_AXI_0_awregion(PMC_NOC_AXI_0_awregion),
    .PMC_NOC_AXI_0_awsize(PMC_NOC_AXI_0_awsize),
    .PMC_NOC_AXI_0_awuser(PMC_NOC_AXI_0_awuser),
    .PMC_NOC_AXI_0_awvalid(PMC_NOC_AXI_0_awvalid),
    .PMC_NOC_AXI_0_bready(PMC_NOC_AXI_0_bready),
    .PMC_NOC_AXI_0_rready(PMC_NOC_AXI_0_rready),
    .PMC_NOC_AXI_0_wdata(PMC_NOC_AXI_0_wdata),
    .PMC_NOC_AXI_0_wid(PMC_NOC_AXI_0_wid),
    .PMC_NOC_AXI_0_wlast(PMC_NOC_AXI_0_wlast),
    .PMC_NOC_AXI_0_wstrb(PMC_NOC_AXI_0_wstrb),
    .PMC_NOC_AXI_0_wuser(PMC_NOC_AXI_0_wuser),
    .PMC_NOC_AXI_0_wvalid(PMC_NOC_AXI_0_wvalid),
    .PMC_NOC_AXI_0_arready(PMC_NOC_AXI_0_arready),
    .PMC_NOC_AXI_0_awready(PMC_NOC_AXI_0_awready),
    .PMC_NOC_AXI_0_bid(PMC_NOC_AXI_0_bid),
    .PMC_NOC_AXI_0_bresp(PMC_NOC_AXI_0_bresp),
    .PMC_NOC_AXI_0_buser(PMC_NOC_AXI_0_buser),
    .PMC_NOC_AXI_0_bvalid(PMC_NOC_AXI_0_bvalid),
    .PMC_NOC_AXI_0_rdata(PMC_NOC_AXI_0_rdata),
    .PMC_NOC_AXI_0_rid(PMC_NOC_AXI_0_rid),
    .PMC_NOC_AXI_0_rlast(PMC_NOC_AXI_0_rlast),
    .PMC_NOC_AXI_0_rresp(PMC_NOC_AXI_0_rresp),
    .PMC_NOC_AXI_0_ruser(PMC_NOC_AXI_0_ruser),
    .PMC_NOC_AXI_0_rvalid(PMC_NOC_AXI_0_rvalid),
    .PMC_NOC_AXI_0_wready(PMC_NOC_AXI_0_wready)
  );
endmodule
